H. Meyr

Optimum vectorization of scalable synchronous dataflow graphs

For the design of complex digital signal processing systems, block diagram oriented synthesis of real time software for programmable target processors has become an important design aid. The synthesis approach discussed in this paper is based on multirate block diagrams with scalable synchronous dataflow (SSDF) semantics. For this class of dataflow graphs optimum vectorization techniques are introduced. Vectorization is treated as a transformation on an SSDF graph which increases the number of samples consumed or produced per activation of a block according to a specific optimization criterion. The presented optimization criterion jointly minimizes context-switching overhead caused by an activation of a block and maximizes the degree of vector processing of the important class of single appearance minimum activation schedules (SAMAS). This class comprises schedules in which each block appears exactly once and is activated minimum times. First, single appearance implies the most compact implementation of a schedule in terms of program memory. Second, minimum activation implies increased throughput according to optimum vectorization and minimal context-switching.<<ETX>>

A fully digital feedforward MSK demodulator with joint frequency offset and symbol timing estimation for burst mode mobile radio

A strictly feedforward demodulator structure for minimum shift keying (MSK) modulation with joint nondata-aided symbol clock and frequency offset estimation is presented. Due to its feedforward operation, clock synchronization and frequency offset compensation are hang-up free, and the demodulator is well suited for a digital implementation. The sampled baseband signal is passed through a nonlinearity and smoothed by a digital filter. The magnitude of the filter output directly drives the clock recovery process. The phase of the smoothed signal is an estimate of the carrier frequency offset and is used for offset compensation. Following synchronization, the signal is demodulated by differentially coherent detection. The performance of the demodulator is assessed for the AWGN and the Rayleigh flat and frequency-selective fading channel by computer simulations. >

Maximum likelihood open loop carrier synchronizer for digital radio

The problem of carrier synchronization frequency offset is considered. New frequency estimation algorithms for the data-aided (DA), the decision directed (DD), and the nondata-aided (NDA) mode are derived from the maximum likelihood principle. Their performance is assessed by both analysis and simulation, and the error variance is compared to the Cramer-Rao bound. The resulting open-loop system for estimating and correcting frequency and carrier phase for a coherent M-ary phase shift keying (MPSK) transmission system is presented and verified. Implementation issues like filter functions and nonlinearities are addressed. It is found that the proposed structures provide optimal synchronization at high SNR and robust synchronization even at low SNR.<<ETX>>

An all feedforward synchronization unit for digital radio

The complete structure of a fully digital all feed forward synchronization unit is presented, establishing clock and carrier synchronization. Although the basic synchronization concept is able to operate solely on random data, a structure is presented which is tailored to spontaneous packet transmission and time division multiple access (TDMA) applications, where additional frame synchronization has to be performed. It is shown that frame and frequency synchronization can be efficiently combined. The key features of the scheme, which are presented in terms of estimation error variances and bit error rate (BER), ensure high speed synchronization with negligible decoder performance degradation.

Map channel decoding: Algorithm and VLSI architecture

The symbol by symbol MAP algorithm is parallelized leading to a purely feedforward block processing architecture for high speed soft output channel decoding. Using a novel algebraic formulation of the MAP algorithm, an algorithmic modification is discussed resulting a large decrease in complexity. A concatenated decoding system employing the soft output MAP algorithm compares favorably with parallel Viterbi decoders using a standard code, which is proved by a high speed system example.<<ETX>>

Soft-output Viterbi decoding: VLSI implementation issues

The soft-output Viterbi algorithm (SOVA) is a decoding algorithm which uses soft quantized inputs and delivers soft decision outputs. Implementation parameter effects in SOVA decoding that are related to considerable variations in area consumption of VLSI implementations are considered, i.e., the quantization of the reliability values inside the survivor memory unit, the depth of reliability updating, and the effect of a simplified update rule on the reliability values. Results of extensive simulations are presented. Area estimates obtained by logic synthesis from VHSIC hardware description language (VHDL) descriptions are given to show how these parameters translate into the area consumption of VLSI implementations.

Optimum frame synchronization for asynchronous packet transmission

The optimum decision rule for one-shot packet frame synchronization in additive white Gaussian noise is derived. The optimum decision rule takes into account known symbols preceding the frame synchronization word used for startup carrier and timing synchronization. A simpler-to-implement high signal-to-noise ratio approximation is given. The derived decision rules are compared to the correlation rule and to an approximate maximum likelihood (ML) decision rule designed for periodic packet transmission. Simulation results show that the performance of the various decision rules strongly depends on the absolute synchronization position. The correlation rule shows unacceptable performance for short synchronization words.<<ETX>>

Two frequency estimation schemes operating independently of timing information

Proposes two novel carrier frequency estimation schemes which are well suited for a fully digital receiver. Both algorithms are able to cope with frequency offsets in the range of 100% and more without requiring that clock synchronization has to be performed in advance or that known symbols are available. The authors analyze and compare their performance in terms of their acquisition speed as well as in terms of the estimation error mean and variance. Computer simulations are used to verify the analysis.<<ETX>>

Carrier frequency recovery for a fully digital direct-sequence spread-spectrum receiver: A comparison

A family of different structures for carrier frequency estimation and correction in fully digital direct-sequence spread-spectrum (DS/SS) receivers for M-ary phase shift keying (MPSK)-modulated signals is presented. The performance of the proposed structures is compared analytically as well as by computer simulation. Among the different estimators, feedforward structures are shown to yield near-optimum bit-error performance at moderately large carrier frequency offsets. Furthermore, the use of feedforward estimators allows the design of digital DS/SS modems showing superior acquisition behavior. The simplicity of the involved operations makes the presented structures attractive for VLSI implementation.

Systematic design optimization of a competitive soft-concatenated decoding system

Due to the advances in VLSI technology complete digital communication systems can today be implemented on single application specific VLSI circuits. The optimum choice of implementation parameters, such as signal wordlengths, is a critical design task since poor parameter choices can lead to costly designs. On the other hand, the high number of parameters to be selected span a large search space that is very difficult to handle. The authors present a new systematic approach to parameter selection and apply this approach to the design optimization of a decoding system for a concatenated coding scheme. Two convolutional codes are concatenated and both are decoded by soft decision decoding. This is facilitated by means of soft output decoding of the inner code. The performance of the scheme is better than that of the well known standard code with 64 states for moderate BER at equivalent implementation cost. The proposed coding scheme is thus an attractive alternative whenever high bit error rate performance is prerequisite, e.g. for digital HDTV transmission.<<ETX>>