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Dive into the research topics where H. Sakaue is active.

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Featured researches published by H. Sakaue.


Electrochemical and Solid State Letters | 2004

Self-organization of a porous alumina nanohole array using a sulfuric/oxalic acid mixture as electrolyte

S. Shingubara; Kazunori Morimoto; H. Sakaue; Takayuki Takahagi

The possibility of fabricating a highly regular nanohole array using different acid mixtures for the anodic oxidation of aluminum was investigated. The regularity of a nanohole array formed using a 1:1 sulfuric/oxalic acid mixture was quantified. Excellent regularity was obtained at around an anode voltage of 32 to 36 V. Cell pitch of the nanohole array at 36 V was 73 nm, which falls between those obtained using sulfuric acid (65 nm at 28 V) and oxalic acid (95 nm at 40 V). The present results strongly suggest that the pitch of the regular nanohole array can be varied by changing the ratio of the different acids.


Solid-state Electronics | 1999

Two-dimensional nanowire array formation on Si substrate using self-organized nanoholes of anodically oxidized aluminum

S. Shingubara; O Okino; Y Sayama; H. Sakaue; Takayuki Takahagi

Abstract A highly ordered two-dimensional array of 48 nm Cu wires was successfully fabricated on Si substrate by the usage of anodic oxidation of aluminum (Al) for the first time. Anodic oxidation was carried out for Al sputtered film on Si substrate covered by a thin thermally oxidized SiO2 film, which was very effective to protect Si substrate from anodic oxidation. A highly ordered array of nanoholes was formed by the two steps Al anodic oxidation, and finally Cu was deposited by electroless plating in nanoholes which aspect ratio was 2.5. The present method suggests possibility of a large area two-dimensional array of quantum dots or wires on semiconductor substrate, which are considered to be a key technology for future ULSIs operated by single electron tunneling phenomena.


Electrochemical and Solid State Letters | 2003

Electroless Plating of Copper on Metal-Nitride Diffusion Barriers Initiated by Displacement Plating

Zenglin Wang; T. Ida; H. Sakaue; S. Shingubara; Takayuki Takahagi

Copper is deposited on TaN and WN barrier layers by electroless plating without the need for activation preprocessing when substrates are (i) pretreated by wet chemical etching to remove surface oxides, and (ii) immersed in an electroless Cu plating solution containing glyoxylic acid as a reducing agent. Electrical potential measurements indicate that the redox potentials of TaN and WN in the plating solution are lower than that of copper, driving displacement plating of Cu in the initial stage of deposition. The adhesion between electroless-plated Cu and the TaN barrier layer after annealing is 0.11 kgf/cm as determined by a peeling test, which is sufficient for reliability during chemical mechanical polishing. A damascene Cu interconnect was successfully fabricated without delamination and exhibited an electrical resistivity of 2.2 μΩ cm after annealing for a 0.42 μm wide interconnect track. These results indicate that the proposed electroless process is suitable for the formation of a Cu seed layer prior to electrodeposition for the fabrication of ultralarge scale integrated interconnects.


Applied Physics Letters | 2001

Atomic-scale defect control on hydrogen-terminated silicon surface at wafer scale

H. Sakaue; Shinya Fujiwara; Shoso Shingubara; Takayuki Takahagi

We have developed a wet preparation method for an atomically defect-free Si wafer surface. In the conventional atomically smooth treatment using ammonium fluoride aqueous solution, dissolved oxygen has been revealed to form defects on the Si (111) surface. We have been able to create an extremely atomically smooth hydrogen-terminated surface with a good periodic step/terrace structure. Moreover, the ordered surface structure was confirmed to be fabricated all over the wafer surface. The atomic-scale defect-free hydrogen-terminated wafer surface with a periodic step/terrace structure is expected to be highly useful as a well-defined substrate for nanostructure fabrication and high-quality film deposition, and to be useful in many other research fields.


Thin Solid Films | 1993

Digital etching study and fabrication of fine Si lines and dots

Jiro Yamamoto; Takashi Kawasaki; H. Sakaue; Shoso Shingubara; Y. Horiike

Abstract For the goal of damage-free microfabrication, digital etching in which one or a few atomic layers are removed with minimum reaction energy has been studied. The atomic layer etching of Si(100) was achieved by the precise control of F atom adsorption. To evaluate sidewall etching damage, conductance for lines fabricated on SIMOX was measured at 4.2 K. Lines fabricated by the digital method exhibited no appreciable damage, contrary to the 0.2 μm line fabricated by magnetron reactive ion etching. In a 0.1 μm line subjected partly to an exposure of hydrogen plasma, non-linearity in the I–V relationship was observed at 4.2 K. The fabrication of Si dots with 20–100 nm diameter was successfully achieved by both an adequate electron beam dose and Ar+ irradiation time. Photoluminescence measurements revealed that a significant plastic deformation was generated in oxidized Si dots on SIMOX substrate.


Applied Physics Letters | 1990

Digital chemical vapor deposition of SiO2

M. Nakano; H. Sakaue; H. Kawamoto; A. Nagata; Masataka Hirose; Y. Horiike

The repetitive cycles of a few monolayers hydrogenated silicon deposition and its oxidation has been employed for the growth of SiO2. The surface reaction is promoted by an alternate irradiation of silicon hydride radical beam produced by the upstream pulsed microwave discharge of SiH4 and discharged oxygen beam. The deposition rate is controlled by the flow velocity of silane gas jet and substrate temperature. It is shown that the deposition species ejected with supersonic velocity into a high vacuum reactor conformably fills the SiO2 film into a deep Si trench.


international electron devices meeting | 2003

Bottom-up fill of copper in high aspect ratio via holes by electroless plating

Shoso Shingubara; Zenglin Wang; Osamu Yaegashi; Ryo Obata; H. Sakaue; Takayuki Takahagi

We succeeded in the bottom-up filling of Cu by electroless plating for the first time. Essential points of this technology are the use of an ultra-thin ICB-Pd catalytic layer and the addition of an adequate amount of sulfopropyl sulfonate inhibiter (SPS) to the electroless plating bath. The adhesion strength of the electroless-plated Cu was strong enough to endure against CMP processing, and a 100 nm diameter via hole with 800 nm depth was completely filled by electroless plating only.


MRS Proceedings | 1994

Electromigration Characteristics of Cu and Al Interconnections

Shoso Shingubara; Kazuyuki Fujiki; Atsushi Sano; H. Sakaue; Y. Horiike

Electromigration activation energies (Ea) of Al and Cu interconnections are strongly dependent on the grain boundary morphology, and it is pointed out that Ea of bamboo-like Al interconnection is not less than Ea of small grain Cu interconnections. Small resistance oscillatory changes caused by electromigration, which are classified into three categories; oscillation, downward spikes, and upward spikes, are investigated in detail. It seems most likely that oscillations correspond to annihilation and formation of the one void. It is also pointed out that downward spikes are local, while upward spikes are non-local. Dislocation dynamics such as generation, rapid transport and subsequent annihilation are considered to be origins of spikes.


Japanese Journal of Applied Physics | 1995

Fabrication and Evaluation of Three-Dimensional Optically Coupled Common Memory

Kouji Miyake; Tohru Namba; Kenji Hashimoto; H. Sakaue; Seiichi Miyazaki; Y. Horiike; Shin Yokoyama; Mitsumasa Koyanagi; Masataka Hirose

A three-dimensional optically coupled common memory (3D-OCC memory) test chip, on which GaAs LEDs are integrated using the microbonding technique, has been fabricated using a 2 µ m complementary metal-oxide-semiconductor (CMOS) technology. Static memory cell circuits with photodiodes were formed on the chip. Optical writing and electrical reading operations of the 3D-OCC memory test chip have been demonstrated.


STRESS-INDUCED PHENOMENA IN METALLIZATION: Sixth International Workshop on Stress-Induced Phenomena in Metallization | 2002

Evaluation of temperature rise due to joule heating and preliminary investigation of its effect on electromigration reliability

Shoso Shingubara; Seiichi Miyazaki; H. Sakaue; Takayuki Takahagi

A demand to increase current density of ULSI interconnections with shrinkage of feature sizes inevitably brings about temperature rise due to Joule heating. We studied how temperature distribution changes with an increase in the current density and further investigated its effect on electromigration-induced failures. We evaluated a temperature rise in a single level Al-alloy interconnection by the use of IR-CCD camera and 3-D fluid dynamical finite element analysis. A build-up of a significant temperature gradient was observed with an increase in the current density. Failure analysis of electromigration accelerating tests revealed that the degradation of MTF at high current density conditions was due to occurrence of a new failure mode of “evaporation mode.” The evaporation mode is most likely caused by an annihilation of a void. Further discussions concerning the relationship between the evaporation mode and the Joule heating effect are given.

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Zenglin Wang

Shaanxi Normal University

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