H. Schellevis

A back-wafer contacted silicon-on-glass integrated bipolar process. Part I. The conflict electrical versus thermal isolation

A novel silicon-on-glass integrated bipolar technology is presented. The transfer to glass is performed by gluing and subsequent removal of the bulk silicon to a buried oxide layer. Low-ohmic collector contacts are processed on the back-wafer by implantation and dopant activation by excimer laser annealing. The improved electrical isolation with reduced collector-base capacitance, collector resistance and substrate capacitance, also provide an extremely good thermal isolation. The devices are electrothermally characterized in relationship to different heat-spreader designs by electrical measurement and nematic liquid crystal imaging. Accurate values of the temperature at thermal breakdown and thermal resistance are extracted from current-controlled Gummel plot measurements.

Extraction and modeling of self-heating and mutual thermal coupling impedance of bipolar transistors

A measurement system comprised of an ultra-low-distortion function generator, lock-in amplifier, and semiconductor parameter analyzer is used for sensitive extraction of the small-signal thermal impedance network of bipolar devices and circuits. The extraction procedure is demonstrated through measurements on several silicon-on-glass NPN test structures. Behavioral modeling of the mutual thermal coupling obtained by fitting a multipole rational complex function to measured data is presented.

Large Polycrystalline Silicon Grains Prepared by Excimer Laser Crystallization of Sputtered Amorphous Silicon Film with Process Temperature at 100 °C

Large polycrystalline silicon (poly-Si) grains with a diameter of 1.8 µm are successfully prepared by excimer laser crystallization (ELC) of a sputtered amorphous silicon (α-Si) film at a maximum process temperature of 100 °C. By pulsed DC magnetron sputtering, α-Si is deposited on a non-structured oxidized wafer. It is found that the α-Si film deposited with a bias is easily ablated during ELC, even at an energy density below the super lateral growth (SLG) region. However, the α-Si film deposited without a bias can endure an energy density well beyond the SLG region without ablation. This zero-bias sputtered α-Si film with a high compressive stress has a low Ar content and a high density, which is beneficial for the suppression of ablation. Large grains with a petal-like shape can be obtained in a wide energy density window, which can be a result from some fine crystallites in the α-Si matrix. These large grains with a low process temperature are promising for the direct formation of system circuits as well as a high-quality display on a plastic foil.

Silicon micromachining of high aspect ratio, high-density through-wafer electrical interconnects for 3-D multichip packaging

This paper presents a novel silicon micromachining method, which combines tetra methyl ammonium hydroxide (TMAH) etching and deep-reactive ion etching (DRIE) along with bottom-up copper electroplating, to fabricate high-density and high-aspect ratio through-wafer electrical interconnects (TWEIs) for three-dimensional multichip packaging. The silicon wafer was locally etched with TMAH from the backside until the desired membrane thickness was reached, and then DRIE was performed on the membrane until the holes were etched through. TMAH etching preserved large areas of the wafers at the original thickness, thus, ensuring relatively strong mechanical strength and manipulability. DRIE made it possible to realize high-aspect ratio holes with minimized wafer area consumption. A new bottom-up copper electroplating technique was developed to fill the high-aspect ratio through-wafer holes. This method can avoid seams and voids while achieving attractive electrical features. Through-wafer holes, as small as 5 mum in diameter, have been realized by using the combination of TMAH and DRIE, and have been completely and uniformly filled by using bottom-up copper electroplating

RF power silicon-on-glass VDMOSFETs

Applicability of vertical double-diffused MOSFETs for future base station power amplifiers has been demonstrated by characterizing the first devices fabricated in a substrate transfer silicon-on-glass technology. For a gate length of 0.8 /spl mu/m and gate width of 350 /spl mu/m, the measured f/sub T//f/sub max/ is 6/10 GHz, and the breakdown voltage approaches 100 V. The devices feature an output power of 12 dBm at the 1-dB compression point, excellent linearity (IM3/IM5 of -50/ -70 dBc at 10-dB backoff) and high power gain (14 dB) at 2 GHz, and are the first vertical DMOSFETs suitable for 2-GHz power applications. Excellent heat sinking and no significant degradation of the quiescent current due to hot-carrier injection ensure thermal stability and good long-term reliability of the fabricated devices.

Ultra Linear Low-Loss Varactor Diode Configurations for Adaptive RF Systems

Two linear low-loss varactor configurations for tunable RF applications are compared. The wide tone-spacing varactor stack provides the best linearity for signals with relative large tone spacing like receiver jammer situations. The narrow tone-spacing varactor stack offers the highest linearity for in-band-modulated signals, and is better suited to adaptive transmitters. Both structures make use of a varactor with an exponential C(VR) relation, and so the different requirements of transmit and receive chains can be addressed in one technology. Both configurations have been realized in a silicon-on-glass technology. The measured Q at 1.95 GHz is from ~ 40 to 200 over a capacitance tuning range of 3.5 with the maximum control voltage of 12 V. The measured OIP3 of both structures are roughly 60 dBm.

Bulk-Micromachined Test Structure for Fast and Reliable Determination of the Lateral Thermal Conductivity of Thin Films

A novel bulk-micromachined test structure is presented for the fast and reliable determination of the lateral thermal conductivity of thin films. The device is composed of a heater resistor and thermocouples that are fabricated in polysilicon (poly-Si), and the associated processing and DC measurement procedures are straightforward. The validity of the method is supported by numerical simulations and verified by experimental determination of the lateral thermal conductivity of aluminum (Al), aluminum nitride (AlN), p-doped poly-Si, and silicon nitride (SiN) thin films. For Al, an average value of 217 W m-1 K-1 was found for 1-mum thick layers. For the other layers, a number of thicknesses were studied, and the increase of thermal conductivity with thickness was effectively detected: for AlN, values from 7 to 11.5 W m-1 K-1 were found, and for p-doped poly-Si, values went from 21 to 46 W m-1 K-1 for thicknesses from 0.15 to 1 mum. For SiN, a value of 1.8 was extracted for layers thicker than 0.5 mum.

Improved RF Devices for Future Adaptive Wireless Systems Using Two-Sided Contacting and AlN Cooling

This paper reviews special RF/microwave silicon device implementations in a process that allows two-sided contacting of the devices: the back-wafer contacted silicon-on-glass (SOG) substrate-transfer technology (STT) developed at DIMES. In this technology, metal transmission lines can be placed on the low-loss glass substrate, while the resistive/capacitive parasitics of the silicon devices can be minimized by a direct two-sided contacting. Focus is placed here on the improved device performance that can be achieved. In particular, high-quality SOG varactors have been developed and an overview is given of a number of innovative highly-linear circuit configurations that have successfully made use of the special device properties. A high flexibility in device design is achieved by two-sided contacting because it eliminates the need for buried layers. This aspect has enabled the implementation of varactors with special Ndx -2 doping profiles and a straightforward integration of complementary bipolar devices. For the latter, the integration of AlN heatspreaders has been essential for achieving effective circuit cooling. Moreover, the use of Schottky collector contacts is highlighted also with respect to the potential benefits for the speed of SiGe heterojunction bipolar transistors (HBTs).

High-performance varactor diodes integrated in a silicon-on-glass technology

High-performance low-loss boron-passivated Schottky varactor diodes have been fabricated in a silicon-on-glass substrate transfer technology, using laser-annealed back-wafer contacts and copper-plated aluminum. The diodes have well-defined doping profiles predetermined by the circuit application and high quality factors ranging typically from 100 till 300 at 2 GHz.

Sub-500/spl deg/C solid-phase epitaxy of ultra-abrupt p/sup +/-silicon elevated contacts and diodes

A well-controlled low-temperature process, demonstrated from 350/spl deg/C to 500/spl deg/C, has been developed for epitaxially growing elevated contacts and near-ideal diode junctions of Al-doped Si in contact windows to the Si substrate. A physical-vapor-deposited (PVD) amorphous silicon layer is converted to monocrystalline silicon selectively in the contact windows by using a PVD aluminum layer as a transport medium. This is a solid-phase-epitaxy (SPE) process by which the grown Si is Al-doped to at least 10/sup 18/ cm/sup -3/. Contact resistivity below 10/sup -7/ /spl Omega//spl middot/cm/sup 2/ is achieved to both p/sup -/ and p/sup +/ bulk-silicon regions. The elevated contacts have also been employed to fabricate p/sup +/-n diodes and p/sup +/-n-p bipolar transistors, the electrical characterization of which indicates a practically defect-free epitaxy at the interface.