H. Verweij

A fast and flexible data acquisition system for multiwire proportional chambers and other detectors

Abstract A system is described which can handle high input rates and provide very short read-out times. The delay element is a twisted-pair cable. ECL 10k circuitry is used throughout, part of which is hybridized. The non-destructive and fast read-out makes the system attractive for experiments with data pre-processing. Typical read-out time is ⋍120 ns per coded 16-bit data word. One crate contains a maximum of 704 channels, and up to 16 crates may be chained on a branch. Further expansion is possible by the use of several branches. Additional modules provide for the following: reading of multiple branches, multiple outputs of processed data, reading of several systems via one CAMAC interface, normalized data for chamber and cluster identification, and burst buffering.

Electronics and results for the central detector

Abstract The electronics systems for the readout of a large drift chamber (25 m3, 6110 sense wires) with image readout, to be used at the CERN p - p collider, is described. The system uses a flash analog-to-digital converter and is able to measure directly the drift time, the charge division, and the energy losses for many tracks on each wire. The results obtained with chamber and electronics prototypes are reported.

AN AMPLIFIER, TRIGGER, AND MEMORY FOR SIGNALS FROM PROPORTIONAL WIRE CHAMBERS.

Abstract A circuit has been developed for the amplification and storage of signals from proportional wire chambers. The input sensitivity is ≈0.4 mV and the input impedance ≈2 k ω .

Multiple time digitizers and a trigger system for drift chambers

The architecture of a readout system is described which will be used in conjuction with the muon detector in the UA-1 experiment at the pp collider at CERN. In addition to measuing drift time for spatial information, the system provides a fast trigger (<1 μs after drift time) and a second level trigger decision based on a fast microprocessor. The fast trigger part allows the use of the muon detetor as an active trigger element, while a second level trigger decision using the detailed digitizer data is included for adequate reduction of the trigger rate. The multiple time digitizer (MTD) is based on the use of fast RAMs (256 × 4) as 125 MHz shift registers, giving time bins of 8 ns and a time range of 2 μs (256 × 8 ns). The high input rate has imposed a fast readout and transfer to a buffer in the controller. The data in this buffer is reordered according to wire number and corresponding times. Together with look-up tables this allows fast processing of the data for a second level trigger.

A photomultiplier pulse shaper with minimal time slewing, incorporating a tunnel diode cascade trigger circuit

Abstract An instrument is described that converts signals from photomultipliers into pulses of standard amplitude (10 mA) and adjustable width (2.5–100 ns). It consists of an input shaping network, of which two versions are given, and a tunnel diode cascade trigger circuit. An attempt has been made to reduce the time slewing to a minimum: with input pulses ranging from 10–160 mA, from a 56 AVP photomultiplier, it remains within ±0.25 ns. The instrument is capable of working up to frequencies of 150 Mc/sec.

Multiple time digitizers and a trigger system for drift chambers – a complement

Abstract Reliable operation of RAMs as shift registers can be obtained up to frequencies exceeding 125 MHz using standard binary coded addressing.

A circuit for proceesing signals from multiwire proportional chambers constructed in thick film hybrid form

Abstract A hybrid circuit for multiwire proportional chambers is described. It provides amplification, discrimination, delay and storage of wire signals. Results of tests on prototypes are given.

A fast transistorized discriminator

A fast transistorized discriminator is described. The threshold can be varied from 100 mV to 2.1 V. Stable operation is obtained for rates up to at least 10 Mc/s. The unit gives a negative output pulse of 2.5–3 V and a positive of 9 V, both into 125 Θ .

A tunnel diode cascade circuit

Abstract A new method is described to combine the input sensitivity and stability of a low peak current tunnel diode with the high power output of a high peak current tunnel diode, by connecting tunnel diodes and back diodes in cascade.

A 100 Mc/s DISCRIMINATOR AND SCALER

The discriminator and scaler described are capable of handling up to 4 x 10/sup 6/ pulses per machine burst of 200 msec length and scaling up to 5 pulses in a period of about 50 nsec. Primarily the instrument is a scaler, and by equalizing the sensitivity of the two states of the first bistable discriminator action is obtained. The bistables are made with transistors rather than tunnel diodes. The scaler consists of three cascaded binary stages. Circuit diagrams of the threshold amplifier and scaler are shown. Curves show the resolving time, threshold vs input pulse, and threshold vs temperature. In use at the CERN proton synchrotron, these instruments performed reliably over long periods. (A.G.W.)