H. Ziad

Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as the bonding and sealing material. Measurements show that the influence of the wafer-level package on the RF performance can be made very small.

An industrial process for 650V rated GaN-on-Si power devices using in-situ SiN as a gate dielectric

This paper reports on an industrial DHEMT process for 650V rated GaN-on-Si power devices. The MISHEMT transistors use an in-situ MOCVD grown SiN as surface passivation and gate dielectric. Excellent off-state leakage, on-state conduction and low device capacitance and dynamic Ron is obtained. Initial assessment of the intrinsic reliability data on the in-situ SiN is provided.

Impact of Ti/Al atomic ratio on the formation mechanism of non-recessed Au-free Ohmic contacts on AlGaN/GaN heterostructures

The formation mechanism of non-recessed Au–free Ohmic contacts on the AlGaN/GaN heterostructures is investigated for various Ti/Al atomic ratios (Al–rich versus Ti–rich) and annealing temperatures ranging from 500 to 950 °C. It is shown that Ti/Al atomic ratio is the key parameter defining the optimum annealing temperature for Ohmic contact formation. Ti–rich contacts processed at high temperature result in low contact resistance ∼0.7 Ω mm, better to those obtained at low temperature or with Al–rich metal stacks. The variation of the contact resistance with Ti/Al atomic ratio and annealing temperature is correlated with the intermetallic phase changes and interfacial reaction. Depending on the Ti/Al atomic ratio, two distinct mechanisms can be distinguished. For a small quantity of Ti (e.g., Al–rich contacts), Ohmic contact formation is done through a weak interfacial reaction which is nonexistent at high temperature due to the degradation of the metal morphology. However, for a quantity of Ti higher than...

ISPSD `07 Best Paper Award; Record-Low On-Resistance for 0.35 μm based Integrated XTREMOS TM Transistors

Experimental data are shown for integrated smart power transistors breaking the silicon limit at 100V. The performance is close to the much lower super-junction limit for the given device pitch. The device uses standard trench technology and is implemented in a 0.35 μm smart power process. Key steps to improve device performance yielding a record performance of 30 mOhm*mm2 for a Vbd of 94V are highlighted in the paper.

Use of Oxynitride Dielectric to Maximise the Growth Rate of Selective Epitaxial Base Layer in a Self-Aligned Double-Polysilicon SiGe Bipolar Transistors

State of the art SiGe BiCMOS processed with a double-polysilicon self-aligned Heterojunction Bipolar Transistor (HBT) is fabricated by means of selective epitaxial deposition. Typically the deposition rate of the epitaxial layer is kept very low to ensure the selectivity. This is having a negative impact on manufacturability and cost. The paper is describing the development, properties and use of a new oxynitride interpoly layer that allows an improvement of growth rate of the selective epitaxial layer by a factor 4 to 5. This development is implemented in an industrial 0.35 µm SiGe BiCMOS technology [1].

An industrial 0.35 /spl mu/m SiGe BiCMOS technology for 5 GHz WLAN featuring an improved selective epitaxial growth process

A SiGe BiCMOS process with a double-polysilicon self-aligned Heterojunction Bipolar Transistor (HBT) fabricated by means of selective epitaxy has been developed. The selective epitaxial growth is improved with the use of an innovative oxy-nitride interpoly layer which increases the growth rate. The HBT features a current gain cut-off frequency f/sub T/ of 43 GHz and a maximum available cut-off frequency f/sub MAX/ of 80 GHz at a collector-emitter bias voltage of 3 V. N-p-n transistors are integrated in 0.35 /spl mu/m CMOS process with high quality RF passive components. A Low Noise Amplifier (LNA) designed in this technology for 5 GHz wireless local area networks (WLAN) demonstrated measurement data close to the simulated ones.