Habibullah Jamal

Spectrum sensing techniques for cognitive radio networks: Performance analysis

With the advancements in telecommunication, it is generally believed that we are getting short of spectrum. If we look at frequency usage chart it is practically viewed that spectrum usage is concentrated at some portion while some of frequency bands are left unutilized, means actually we have spectrum abundance problem lies in spectrum management policies. Cognitive radio technology provides the efficient way to utilize the electromagnetic spectrum. Physical layer of cognitive radio provides the facility to sense spectrum to determine the spectrum holes. Literature has presented various techniques to sense the spectrum but still there is room for researchers in this field. This paper provides the implementation issues for several spectrum sensing techniques and performance analysis for energy detection, matched filter detection, cyclotationary feature based detection and eigenvalue based detection.

Cognitive communication device for vehicular networking

This paper presents intelligent Communication protocols for universal access in a proposed Vehicular Networking Device. The device can communicate on multiple frequency bands using different MAC and PHY Interfaces. The device cannot use existing routing protocols as they are limited and work in relation with a unique MAC and PHY Interface. This paper presents the communication protocols and vehicular device that extends the routing protocols to work as a Cognitive layer over multiple MAC and PHY Interface for optimum connectivity, seamless switching and Quality of Service parameters. The device is tested with three extended routing protocols AODV-MI, GOLSR-MI and SORP. The device incorporates integrated multi telecommunication technologies like GSM, Satellite, VHF, UHF, HF, Broadband Wireless and wired links.

An 8-bit systolic AES architecture for moderate data rate applications

The complexity involved in mapping an algorithm to hardware is a function of the controller logic and data path. Minimizing data path size can lead to significant savings in hardware area and power dissipation. This paper presents an implementation of a novel architectural transformation technique for mapping a word bit wide algorithm to byte vector serial architecture. The technique divides the input word to several bytes and then traces each byte for extracting architectural transformation. The technique is applied on Advanced Encryption Standard (AES) algorithm which is non-linear in nature. Using this technique, the 32-bit AES algorithm is transformed into a byte-systolic architecture. The novelty of the technique is more pronounced around the mix column design which is the most complex part of the AES algorithm. The complex matrix multiplication component and standard transformations of the 32-bit AES algorithm are transformed to support 8-bit operations. The resulted AES architectures reuse same logic resources for key expansion and encryption/decryption. The proposed design offers moderate data rates in the range of 41Mbps for encryption and 37Mbps for decryption while utilizing 236 and 280 slices, respectively, on Xilinx Virtex II xc2v1000-6 FPGA. Comparison results show significant gain in throughput when compared with other 8-bit designs. This makes it a viable data/communication security solution for a variety of embedded and consumer electronics.

Employing Multiple Unmanned Aerial Vehicles for Co-Operative Path Planning:

Abstract In this paper, we work to develop a path planning solution for a group of Unmanned Aerial Vehicles (UAVs) using a Mixed Integer Linear Programming (MILP) approach. Co-operation among team members not only helps reduce mission time, it makes the execution more robust in dynamic environments. However, the problem becomes more challenging as it requires optimal resource allocation and is NP-hard. Since UAVs may be lost or may suffer significant damage during the course of the mission, plans may need to be modified in real-time as the mission proceeds. Therefore, multiple UAVs have a better chance of completing a mission in the face of failures. Such military operations can be treated as a variant of the Multiple Depot Vehicle Routing Problem (MDVRP). The proposed solution must be such that m UAVs start from multiple source locations to visit n targets and return to a set of destination locations such that (1) each target is visited exactly by one of the chosen UAVs (2) the total distance travelled by the group is minimized and (3) the number of targets that each UAV visits may not be less than K or greater than L.

A navigation device with MAC supporting multiple physical networks for extended coverage and operations

This paper presents a novel consumer device that seamless integrates a VHF/UHF radio based mobile ad hoc network with GSM and Satellite networks. The device possesses the capability of operating in a wireless environment where multiple media covers patches of specified areas. The device acts like a universal communication gateway incorporating an intelligent communication controller and multiple physical interfaces for extended coverage. The controller is a cognitive cross-layer design that automatically selects and switches to most optimal network technology based on pre-defined Quality of Service criteria. This cognitive controller keeps communicating nodes connected to the vehicular network. A hybrid zone based QoS aware routing mechanism for multiple physical interfaces and networks is also presented. The device supports two GSM networks, one Satellite carrier, 802.11 interface and VHF or UHF modems including a GPS receiver. Such devices find applications in emerging Wireless Access in Vehicular Environment.

An Efficient High Throughput FPGA Implementation of AES for Multi-gigabit Protocols

Due to the requirement of high throughput architecture for encrypted channels, an efficient implementation of hardware is needed. This can be achieved by using smart utilization of high end reconfigurable platforms. To achieve convincingly high throughput, an efficient non-pipelined style implementation of Advanced Encryption Standard (AES) with key size of 128-bit, for multigigabit protocols on Field Programmable Gate Array (FPGA)is presented.

Secure cognitive mobile hotspot

The paper presents a novel consumer device that acts as a cognitive mobile hotspot to provide ubiquitous secure wireless WAN and LAN connectivity while on the move. The mobile hotspot acts as a gateway and integrates VHF/UHF radios with multiple wireless WAN and LAN technologies. The device supports GPRS, EDGE, WCDMA, CDMA2000 and WiMAX as WAN interfaces for long range communication and 802.11, Bluetooth and VHF/UHF interfaces for short range communication. The cognitive controller in the device seamlessly switches the WAN interfaces to provide optimum connectivity and Quality of Service parameters to the LAN devices and VHF/UHF radio links. In applications where nodes are fully mobile, the cognitive mobile hotspot acts a centroid by adjusting its position dynamically and provides a complete mobile backbone for optimum connectivity to mobile devices in a heterogeneous environment. The unique device opens a new paradigm of mobile backbone and seamless switching between multiple wireless broadband technologies and integration of wireless LAN and VHF/UHF interfaces. The device finds applications in vehicle area networks, mobile branch offices, mobile healthcare, media & broadcasting, sporting competitions, trade fairs, exhibitions and mission critical applications like flood relief operations and disaster recovery.

Mapping of high-bit algorithm to low-bit for optimized hardware implementation

This paper presents the outcome of a novel technique for mapping a class of high data width algorithms to low data width for efficient hardware implementation. The complexity of mapping an algorithm in hardware directly depends upon the data path size as all the registers and computational blocks depend on this size. Reducing the data path requirement can result in substantial savings in hardware. Folding techniques classically reduce the bit-widths. Our techique reduces the data path width without folding or timesharing the hardware resources. The technique is implemented on the advanced encryption standard (AES) algorithm and substantial savings in hardware cost is reported. Using this technique the 32-bit AES is implemented on a byte-systolic 8-bit architecture. The proposed crypto processor architecture resulted in efficient hardware resource utilization reducing data-path, buses, registers and memories to 8-bits, minimizing control logic, area and power. Unlike commercially available AES architectures, which incorporate separate hardware modules for key expansion, the proposed crypto processor design reuses the same architecture for both key expansion and encryption. The proposed design offers moderately high data rates when mapped on FPGA.

An area efficient interpolation filter for digital audio applications

The paper describes a hardware efficient interpolation filter for portable digital audio applications. The design of the filter is based on merged delay transformation (MDT). Existing MDT based interpolator is efficient in terms of power consumption but its performance drastically degrades in terms of area. The proposed modified MDT interpolator is efficient in terms of both area and power consumption. The comparison of the modified architecture with the original MDT interpolator, existing polyphase FIR and cascaded IIR based interpolators is presented. The significant reduction in area and power consumption makes the modified architecture as a potential candidate for area critical and power efficient digital audio applications.

Realization of IIR decimation filters based on merged delay transformation

A novel realization of IIR decimation filters is proposed which is based on merged delay transformation. The transformation is derived analytically and can be applied directly to first- and second-order IIR filters. Computational efficiency is enhanced because the current output can be directly computed from Mth old output. The output data rate is decreased by M by merging M number of delay elements in the recursive path. The proposed transformation is applied to higher-order IIR filter by decomposing it into parallel first-order and second-order sections. This transformation not only gives better stability for coefficient quantization but also reduces the requirement on processing clock, for sample, rate reduction. Filtering and down sampling are performed in the same stage. Number of multiplications is reduced by 45% as compared to the conventional IIR filters where all output samples are computed.