Haihua Shen

Fast complete memory consistency verification

The verification of an execution against memory consistency is known to be NP-hard. This paper proposes a novel fast memory consistency verification method by identifying a new natural partial order: time order. In multiprocessor systems with store atomicity, a time order restriction exists between two operations whose pending periods are disjoint: the former operation in time order must be observed by the latter operation. Based on the time order restriction, memory consistency verification is localized: for any operation, both inferring related orders and checking related cycles need to take into account only a bounded number of operations. Our method has been implemented in a memory consistency verification tool for CMP (Chip Multi Processor), named LCHECK. The time complexity of the algorithm in LCHECK is O(Cpp2n2) (where C is a constant, p is the number of processors and n is the number of operations) for soundly and completely checking, and O(p3n) for soundly but incompletely checking. LCHECK has been integrated into both pre and post silicon verification platforms of the Godson-3 microprocessor, and many bugs of memory consistency and cache coherence were found with the help of LCHECK.

Coverage Directed Test Generation: Godson Experience

Biased random test generation is one of the most important methods for the verification of modern complex processors. As the complexity of processors grows, the bottleneck remains in generating suitable test programs that meet coverage metrics automatically. Many technologies have been proposed to implement the automatic feedback loop. In this paper, we introduce our coverage directed test generation scheme which combines traditional biased random test generation and genetic algorithms to feed back process. It is the first time we use our scheme in our real industrial processor verification independently and successfully without human intervention. The efficiency of our approach has been demonstrated by the practical results.

CRPG: a configurable random test-program generator for microprocessors

In this paper, we present CRPG, a configurable test-program generator designed for microprocessors. CRPG provides a specification model, which can specify a request that covers the full spectrum between highly directed tests and completely random ones, a test generation engine based on heuristic algorithms, a reference instruction set simulator, and a validation environment, which supports simulation with generated test programs automatically and checks the equivalence of processors and their reference model. CRPG is currently in preliminary use at ICT for the verification of GODSONII - a general RISC microprocessor with more than 2 million logic gates. Experiments show that CRPG can improve the verification process and cut down on skilled manpower requirements considerably.

Empirical design bugs prediction for verification

Coverage model is the main technique to evaluate the thoroughness of dynamic verification of a Design-under-Verification (DUV). However, rather than achieving a high coverage, the essential purpose of verification is to expose as many bugs as possible. In this paper, we propose a novel verification methodology that leverages the early bug prediction of a DUV to guide and assess related verification process. To be specific, this methodology utilizes predictive models built upon artificial neural networks (ANNs), which is capable of modeling the relationship between the high-level attributes of a design and its associated bug information. To evaluate the performance of constructed predictive model, we conduct experiments on some open source projects. Moreover, we demonstrate the usability and effectiveness of our proposed methodology via elaborating experiences from our industrial practices. Finally, discussions on the application of our methodology are presented.

Designing an Effective Constraint Solver in Coverage Directed Test Generation

As the complexity of processors grows, the bottleneck of verification remains in generating suitable test programs that meet coverage metrics automatically. Coverage directed test generation is a technique to automate the feedback from coverage analysis to test generation. It is very important to solve the constraint satisfaction problem for a flexible coverage directed test generator with complex variables. In this paper, we propose an effective constraint solver which combines constraint satisfaction problem’s algorithms and coverage directed test generation to address the challenges that arise from the practical verification problem. We implement the constraint solver in our practical coverage directed test generation platform, which has been used in the verification of an embedded processor. The efficiency of our approach has been demonstrated by the practical results.

Low Power Techniques on a High Speed Floating-point Adder Design

A 64 bit low power, high speed floating-point adder design is presented in this paper. The proposed floating-point adder is based on dual path architecture, and both dynamic and leakage power are reduced by exploiting architecture opportunities to minimize switching activity and maximize the stack effect of the circuits concurrently. Experimental result based on 130 nm CMOS standard cell design shows that average power consumptions of the FP adder can be reduced by 61.4% with proposed low power techniques.

Verification of a configurable processor core for system-on-a-chip designs

The verification of processor cores is very important for SOC design. In this paper we present a verification methodology that extends and enhances the traditional verification methodology to address the configurablility, debugability and other characteristics of processor cores. The proposed methodology has been taken into practice for the verification of a 32-bit embedded processor core - Godson-1 and practice results have proven its flexibility, applicability and good performance

On-the-Fly Reduction of Stimuli for Functional Verification

As a primary method for functional verification of microprocessors, simulation-based verification has received extensive studies over the last decade. Most investigations have been dedicated to the generation of stimuli (test cases), while relatively few has focused on explicitly reducing the redundant stimuli among the generated ones. In this paper, we propose an on-the-fly approach for reducing the stimuli redundancy based on machine learning techniques, which can learn from new knowledge in every cycle of simulation-based verification. Our approach can be easily embedded in traditional framework of simulation-based functional verification, and the experiments on an industrial microprocessor have validated that the approach is effective and efficient.

Estimating design quality of digital systems via machine learning

Although the term design quality of digital systems can be assessed from many aspects, the distribution and density of bugs are two decisive factors. This paper presents the application of machine learning techniques to model the relationship between specified metrics of high-level design and its associated bug information. By employing the project repository (i.e., high level design and bug repository), the resultant models can be used to estimate the quality of associated designs, which is very beneficial for design, verification and even maintenance processes of digital systems. A real industrial microprocessor is employed to validate our approach. We hope that our work can shed some light on the application of software techniques to help improve the reliability of various digital designs.

HTChecker: Detecting hardware trojans based on static characteristics

Hardware Trojan detection, which is very important to the chip security, has drawn more and more attention in both academia and industry. In this paper, we propose a novel hardware Trojan detection scheme named HTChecker, which detects hardware Trojans with subgraph isomorphism based on static characteristics of Trojans. Unlike other schemes, HTChecker pay more attention to preventing the replication and dissemination of hardware Trojans. We evaluate the HTChecker with random mixtures of Trojans and circuits from ITC99 benchmarks and OpenCores. Experiments show that HTChecker can detect Trojans quickly and accurately without “Golden Chip” and it can cope with actual VLSI designs with large scale efficiently.