Haiou Li

Reducing the interface trap density in Al2O3/InP stacks by low-temperature thermal process

By applying low-temperature processes below 300 °C, high-performance Al/Al2O3/InP metal–insulator–semiconductor capacitors with low interface trap density and small capacitance frequency dispersion at the accumulation regime are demonstrated. A minimum interface trap density of 1.2 × 1011 cm−2 eV−1 near the midgap is obtained. The impacts of thermal treatment on interface traps, thermal stability, and interfacial bonding configurations are studied and discussed. It is found that interface trap density could be significantly reduced by removing phosphorus and its oxides at low temperature (250–300 °C), while further increasing the thermal treatment temperature is harmful to interface quality.

Improving breakdown voltage performance of SOI power device with folded drift region

A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.

Novel 700 V high-voltage SOI LDMOS structure with folded drift region

A new high-voltage LDMOS with folded drift region (FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Siactive layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.

A novel multiple super junction power device structure with low specific on-resistance

A novel multiple super junction (MSJ) LDMOS power device is proposed to decrease Ron due to lateral and vertical interactions between the N-pillar and P-pillar. In the studied device: multiple layers of SJ are introduced oppositely under surface SJ; when compared with 2D-depleting of the conventional super junction (CSJ), a 3D-depleted effect is formed in the MSJ thanks to vertical electric field modulation; and, current distribution is improved by deep drain, which increases the drift doping concentration and results in a lower on-resistance. The high electric field around the drain region by substrate-assisted depleted effect is reduced due to the charge balance result from the electric field shielding effect of the bottom SJ, which causes the uniform electric field in the drift region and the high breakdown voltage. The numerical simulation results indicate that the specific on-resistance of the MSJ device is reduced by 42% compared with that of CSJ device, while maintaining a high breakdown voltage; the cell pitch of the device is 12 μm.

The charge islands SOI LDMOS with back-side etching technology

The charge islands SOI LDMOS with Back-side Etching technology structure is proposed. The new structure features the equally spaced charge islands of the upper LDMOS and a back-side etched structure of the lower LDMOS. A series of equidistant high concentration N+ regions are formed at the upper SOI LDMOS by the ion implanting method. The breakdown voltage of the device is improved due to dielectric field enhancement and the interaction of charges. The results show that the breakdown voltage is increased from 210V to 615V (192.8% enhanced), compared to the conventional LDMOS. The on-resistance of the as-studied stacked SOI LDMOS reduces from 48.2 Ω⋅mm2 to 37.23 Ω⋅mm2 comparing with conventional charge islands device, leading to a reduction ratio of 22.7%.

Modification of Al2O3/InP interfaces using sulfur and nitrogen passivations

By focusing on the Al/Al2O3/InP capacitor structure, impacts on interface modification using sulfur and nitrogen passivations against traps and charge formation are systematically investigated. Improved electrical characteristics with low leakage current density, hysteresis, interface trap density, and capacitance frequency dispersion are demonstrated after sulfur or nitride interface passivations. It is clarified that sulfur interface passivation is more effective in reducing the interface traps, while nitride interface passivation shows stronger impact on suppressing the generation of bulk and border traps and the negative interface charges. A possible model based on network modification is proposed to explain the mechanism of the different trap and charge behaviors for sulfur and nitride interface passivation.

Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al

PBTI stress induced interface trap density in buried InGaAs channel n-MOSFETs with InGaP barrier layer and AI₂O₃ dielectric is investigated. DC I_d-V_g measurements show both degradations of positive ΔV_g and sub-threshold swing (S) in the sub-threshold region, also show degradation of positive ΔV_g in the on-current region. The I_d-V_g degradation is mainly contributed by generation of acceptor-like near interface traps under stress.

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PBTI stress induced interface trap density in buried InGaAs channel n-MOSFETs with InGaP barrier layer and AI 2 O 3 dielectric is investigated. DC I d -V g measurements show both degradations of positive ΔV g and sub-threshold swing (S) in the sub-threshold region, also show degradation of positive ΔV g in the on-current region. The I d -V g degradation is mainly contributed by generation of acceptor-like near interface traps under stress.

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By focusing on the Al/Al2O3/InP capacitor structure, impacts on coordination number modification using sulfur and nitride passivations against traps and charge formation are investigated. Improved electrical characteristics with low leakage current density, hysteresis, interface trap density and capacitance frequency dispersion are demonstrated after sulfur or nitride interface passivations. It is clarified that sulfur interface passivation is more effective in reducing the interface traps while nitride interface passivation shows stronger impact in suppressing the generation of bulk and border traps and the negative interface charges. A possible model based on coordination number is proposed to explain the mechanism of the different trap and charge behaviors for sulfur and nitride interface passivations.

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The impact of nitridation and sulfur passivation for In0 53Ga0 47As surfaces on the Al/Al2O3/InGaAs MOS capacitors properties was investigated by comparing the characteristics of frequency dispersion and hysteresis, calculating the Dit and ΔNbt values, and analyzing the interface traps and the leakage current. The results showed that both of the methods could form a passivation-layer on the InGaAs surface. The samples treated by N2 plasma could obtain good interface properties with the smallest frequency dispersion in the accumulation region, and the best hysteresis characteristics and good I–V properties were presented. Also the samples with (NH4/2Sx treatment showed the smallest frequency dispersion near the flat-band region and a minimum Dit value of 2.6 × 1011 cm−2 eV−1.