Haitong Li

A Physics-Based Compact Model of Metal-Oxide-Based RRAM DC and AC Operations

A physics-based compact model of metal-oxide-based resistive-switching random access memory (RRAM) cell under dc and ac operation modes is presented. In this model, the conductive filament evolution corresponding to the resistive switching process is modeled by considering the transport behaviors of oxygen vacancies and oxygen ions together with the temperature effect. Both the metallic-like and electron hopping conduction transports are considered to model the conduction of RRAM. The model can reproduce both the typical I-V characteristics of RRAM in high-/low-resistance state (LRS) and the nonlinear characteristics in LRS. Moreover, to accurately model ac operation mode, the effects of parasitic capacitance and resistance are included in our model. The developed compact model is verified and calibrated by measured data in different HfOx-based RRAM devices under dc and ac operation modes. The excellent agreement between the model predictions and experimental results shows a promising prospect of the future implementation of this compact model in large-scale circuit simulation to optimize the design of RRAM.

A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation

A SPICE model of oxide-based resistive random access memory (RRAM) for dc and transient behaviors is developed based on the conductive filament evolution model and is implemented in large-scale array simulation. The simulations of one transistor-one resistor RRAM array up to 16 kb with wire resistance (Rwire) and capacitance (Cwire) indicate that: 1) resistance-capacitance delay during RESET and leakage current during SET have significant impact on write operations; 2) with array size enlarging, the power dissipation increases during RESET but decreases during SET; and 3) the increased Rwire and Cwire lead to the degradation of high resistance state and the fluctuation of low resistance state, respectively.

A learnable parallel processing architecture towards unity of memory and computing.

Developing energy-efficient parallel information processing systems beyond von Neumann architecture is a long-standing goal of modern information technologies. The widely used von Neumann computer architecture separates memory and computing units, which leads to energy-hungry data movement when computers work. In order to meet the need of efficient information processing for the data-driven applications such as big data and Internet of Things, an energy-efficient processing architecture beyond von Neumann is critical for the information society. Here we show a non-von Neumann architecture built of resistive switching (RS) devices named “iMemComp”, where memory and logic are unified with single-type devices. Leveraging nonvolatile nature and structural parallelism of crossbar RS arrays, we have equipped “iMemComp” with capabilities of computing in parallel and learning user-defined logic functions for large-scale information processing tasks. Such architecture eliminates the energy-hungry data movement in von Neumann computers. Compared with contemporary silicon technology, adder circuits based on “iMemComp” can improve the speed by 76.8% and the power dissipation by 60.3%, together with a 700 times aggressive reduction in the circuit area.

Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model

Resistive switching random access memory (RRAM) is a leading candidate for next-generation nonvolatile and storage-class memories and monolithic integration of logic with memory interleaved in multiple layers. To meet the increasing need for device-circuit-system co-design and optimization for applications from digital memory systems to brain-inspired computing systems, a SPICE model of RRAM that can reproduce essential device physics in a circuit simulation environment is required. In this work, we develop an RRAM SPICE model that can capture all the essential device characteristics such as stochastic switching behaviors, multi-level cell, switching voltage variations, and resistance distributions. The model is verified and calibrated by a variety of electrical measurements on ~10 nm RRAMs. The model is applied to explore a wide range of applications including: 1) variation-aware design; 2) reliability-emphasized design; 3) speed-power assessment; 4) array architecture optimization; and 5) neuromorphic computing. This experimentally verified design tool not only enables system design that utilizes the complete suite of RRAM device features, but also provides solutions for system optimization that capitalize on device/circuit interaction.

Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing

For the first time, a four-layer HfOx-based 3D vertical RRAM, the “tallest” one ever reported, is developed and integrated with FinFET selector. Uniform memory performance across four layers is obtained (±0.8V switching, 106 endurance, 104s@125°C). SPICE simulations show that high drive current of pillar select transistors is required for high-rise 3D RRAM arrays. The four-layer 3D RRAM is a versatile computing unit for (a) brain-inspired computing and (b) in-memory computing. (a) Stochastic RRAM synapses enable robust pattern learning for a 3D neuromorphic visual system. The 3D architecture with dense and balanced neuron-synapse connections provides 55% EDP savings and 74% VDD reduction (enhanced robustness) compared with conventional 2D architecture; (b) in-memory logic such as NAND, NOR, and bit shift, are essential elements for hyper-dimensional computing. Utilizing the unique vertical connection of 3D RRAM cells, these operations are performed with little data movement.

Optimized learning scheme for grayscale image recognition in a RRAM based analog neuromorphic system

An analog neuromorphic system is developed based on the fabricated resistive switching memory array. A novel training scheme is proposed to optimize the performance of the analog system by utilizing the segmented synaptic behavior. The scheme is demonstrated on a grayscale image recognition. According to the experiment results, the optimized one improves learning accuracy from 77.83% to 91.32%, decreases energy consumption by more than two orders, and substantially boosts learning efficiency compared to the traditional training scheme.

Analysis of the Voltage-Time Dilemma of Metal Oxide-Based RRAM and Solution Exploration of High Speed and Low Voltage AC Switching

In this paper, the ac electrical characteristics of metal oxide-based resistive random access memory are investigated based on a developed compact model and the experiment. The voltage-time dilemma phenomenon and the impacts of critical factors on resistive switching speed are addressed. Based on predictions of the model, the small parasitic capacitance, low target high resistance, and large thermal resistance are beneficial to accelerate the resistive switching speed both in SET and RESET processes. The high SET speed and low SET voltage can be achieved by tuning the activation energy of oxygen vacancies. While for the RESET process, the barriers of the release of oxygen ions from electrode and the hopping in resistive switching layer should be turned down simultaneously for high switching speed and low operation voltage.

Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

The ability to learn from few examples, known as one-shot learning, is a hallmark of human cognition. Hyperdimensional (HD) computing is a brain-inspired computational framework capable of one-shot learning, using random binary vectors with high dimensionality. Device-architecture co-design of HD cognitive computing systems using 3D VRRAM/CMOS is presented for language recognition. Multiplication-addition-permutation (MAP), the central operations of HD computing, are experimentally demonstrated on 4-layer 3D VRRAM/FinFET as non-volatile in-memory MAP kernels. Extensive cycle-to-cycle (up to 1012 cycles) and wafer-level device-to-device (256 RRAMs) experiments are performed to validate reproducibility and robustness. For 28-nm node, the 3D in-memory architecture reduces total energy consumption by 52.2% with 412 times less area compared with LP digital design (using registers as memory), owing to the energy-efficient VRRAM MAP kernels and dense connectivity. Meanwhile, the system trained with 21 samples texts achieves 90.4% accuracy recognizing 21 European languages on 21,000 test sentences. Hard-error analysis shows the HD architecture is amazingly resilient to RRAM endurance failures, making the use of various types of RRAMs/CBRAMs (1k ∼ 10M endurance) feasible.

Towards high-speed, write-disturb tolerant 3D vertical RRAM arrays

3D RRAM array suffers more serious reliability issues than 2D array due to the additional dimension involved. This paper systematically assesses the cell-location-dependent write-access (selected cells) and disturbance issues (unselected cells) for a 3D vertical RRAM array. Using a combination of experiments and simulations, a methodology is developed to enable array-level evaluation by conducting single-device measurements and without the need to fabricate a full 3D array. Based on this evaluation method, it is found that a double-sided bias (DSB) scheme improves write-disturb tolerance by a factor of 1800 and reduces write latency by 19 % under worst-case analyses.

Write disturb analyses on half-selected cells of cross-point RRAM arrays

Write disturb on half-selected (HS) cells is investigated through electrical measurements and large-scale array simulations. The experimental results collected from the individual devices under constant stress voltage and consecutive pulse operation are correlated with the HS cells in large-scale arrays based on a physics-based SPICE compact model. The impact of write/read disturb on the HS cells at different locations of the arrays is analyzed. Design guidelines for the optimized array size based on the experimental data and HSPICE simulations are presented: e.g., a 16 kb array can maintain its stored data pattern for 5×106 pulses and will have 164 false bits among half-selected cells after write disturb.