Hajir Hedayati

A 2-GHz Highly Linear Efficient Dual-Mode BiCMOS Power Amplifier Using a Reconfigurable Matching Network

A highly linear, efficient, two-stage power amplifier for high-data-rate wireless applications is presented. The linearity is greatly improved by adding an auxiliary amplifier to the main bipolar transistor amplifier in a feed-forward approach to cancel out the nonlinearity terms. The efficiency enhancement is achieved using a switchable biasing and a reconfigurable output-matching network based on the available input power which is monitored by an on-chip envelope detector. The PA is fabricated using 0.25- μm SiGe:C BiCMOS technology and works at 2 GHz with a supply voltage of 2.5 V. The experimental results show a gain of 13 dB and a maximum output power of 23 dBm with a PAE of 38%. The 1-dB output power compression point is 21 dBm with a 32% PAE. The 6-dB power back-off PAE is 23%. The IM3 and IM5 terms are 41 and 44 dB below the fundamental tone for the 21-dBm output power, respectively. The EVM has been measured to be -30.7 dB at 15-dBm average output power using IEEE 802.16e standard WiMAX 64QAM modulated signal. By employing the linearization technique, EVM and ACLR are improved by 4.5 and 5 dB, respectively, for a WiMAX 64QAM 10-MHz signal bandwidth at 14-dBm average output power.

A 1.8 dB NF Blocker-Filtering Noise-Canceling Wideband Receiver With Shared TIA in 40 nm CMOS

This paper presents a high-performance two-path wideband receiver (RX) for 4G LTE applications. The RX uses an extra GM stage after the LNA to improve the noise figure (NF). Furthermore, different RF and baseband blocker rejection techniques are proposed to significantly improve the linearity of the RX. The blockers are first rejected after the LNA stage through an N-path filter. Then, a novel base-band blocker filtering (BBBF) technique improves IIP3 by 7 dB. A dual-mixer architecture is also employed to attenuate blockers both before and after the mixer stage. The N-path filter noise is sensed out-of-phase by the RX main path and cancelled at the inputs of the shared TIA. The RX achieves 1.8 dB NF with 50 dB gain at 2 GHz in 40 nm CMOS technology. The RX out-of-band IIP3 is +5 dBm, which is improved by 20 dB employing the proposed techniques, while consuming 36 mW.

A 90-nm CMOS UWB Impulse Radio Transmitter With 30-dB In-Band Notch at IEEE 802.11a System

In spite of the FCC regulations, the coexistence of ultra-wideband (UWB) and narrowband (NB) systems is still an unsolved challenge. A UWB transmitter (TX) can severely degrade the performance of an IEEE 802.11a system. In this paper, a fully integrated analog impulse-radio UWB TX is presented that generates a novel UWB pulse with a tunable notch at the frequency of IEEE 802.11a system. The pulse has a 5.5-GHz bandwidth (BW), which makes it suitable for high-resolution high data-rate applications. The TX has a maximum pulse rate of 400 Mpulse/s and energy of 65 pJ/pulse with a power supply of 1.2 V. The measurement results show that the pulse has a 30-dB notch, and the TX power inside the BW of the NB system is less than -78 dBm/MHz. The TX has a biphase modulation and has been fabricated in a 90-nm CMOS process. The proposed pulse meets the Federal Communications Commission mask for UWB systems.

A 0.62–10GHz CMOS dielectric spectroscopy system for chemical/biological material characterization

A CMOS wideband dielectric spectroscopy system is proposed for chemical and biological material characterization. The complex permittivity detection is performed using a configurable harmonic-rejecting receiver capable of indirectly measuring the complex admittance of sensing capacitor exposed to the material-under-test (MUT) and subject to RF signal excitation with a frequency range of 0.62-10GHz. The sensing capacitor is embedded in a voltage divider topology with a fixed capacitor and the relative variations in the magnitude and phase of the voltages across the capacitors are used to find the real and imaginary parts of the permittivity. The sensor achieves an rms permittivity error of less than 1% over the entire operation bandwidth.

A +22dBm IIP3 and 3.5dB NF wideband receiver with RF and baseband blocker filtering techniques

The real challenge in designing wide-band receivers is the ability to tolerate out of band blockers. In this paper, different blocker rejection techniques are proposed to significantly improve the linearity. The blockers are first rejected prior to the LNA, then, a novel base-band blocker filtering technique further rejects the blockers at the TIA input. A dual mixer architecture is also employed to further attenuate blockers. Finally, a very low impedance TIA is designed to improve the linearity of the entire receiver chain. The receiver has an IIP3 of +22 dBm and a NF of 3.5 dB in 0.18 μm CMOS technology.

A 3.1–10.6 GHz ultra wide-band impulse radio transmitter with notch implementation for in-band interferers in 90nm CMOS

One of the serious challenges in Ultra Wide-band (UWB) systems is the in-band interferer system in the middle of the UWB band which affects the system performance severely. In this paper an analog in-band interference avoidance IR-UWB transmitter is presented. The fully integrated transmitter generates a novel UWB pulse with a tunable notch at the frequency of 802.11a interferer. The pulse covers the whole UWB spectrum (3.1-10.6 GHz) which makes it suitable for high resolution high data-rate applications. The transmitter has a bi-phase modulation and has been fabricated in IBM 90nm CMOS.

A 1.8 dB NF blocker-filtering noise-canceling wideband receiver with shared TIA in 40nm CMOS

This paper presents a high performance two-path wideband receiver (RX) for mobile applications. The RX uses an extra gain stage after the LNA to significantly improve the noise figure (NF). Furthermore, different RF and baseband blocker rejection techniques are proposed to significantly improve the linearity of the RX. The blockers are first rejected after the LNA stage through an N-path filter. Then, a novel base-band blocker filtering (BBBF) technique improves IIP3 by 7 dB. A dual mixer architecture is also employed to attenuate blockers both before and after the mixer stage. The N-path filter noise is sensed out-of-phase by the main path and cancelled at the inputs of the shared TIA. The RX achieves 1.8 dB NF with 50 dB gain at 2 GHz in 40nm CMOS technology. The RX out-of-band IIP3 is +5 dBm, which is improved by 20 dB by the proposed techniques, while consuming 36 mW.

A CMOS inverse Chebyshev channel selection filter for extravehicular activity (EVA) radio receivers

This paper presents an inverse Chebyshev filter for channel selection in the baseband section of an extravehicular activity (EVA) fully integrated radio receiver. The filter is synthesized from a 4th order doubly-terminated LC ladder prototype using a leapfrog structure in order to minimize the use of active components. The cutoff frequency of the filter is digitally controlled for different channel bandwidths through a binary weighted capacitor bank that allows tuning from 1.1 MHz to 2.28 MHz. The derivation of the filter specifications from the system level parameters of the EVA radio receiver is presented. Also, the impact of the channel selection filter in the overall receiver performance is discussed. The circuit is implemented using the IBM 0.18 μm standard process and post-layout simulations show a pass-band gain of -0.07 dB, an IIP3 of 38 dBm, adjacent channel rejection better than 50 dB and a noise figure of 30.2 dB. The filter operates from a 1.8 V power supply consuming 4.03 mA.

An interferer-tolerant receiver with active feedback for cognitive radio applications

A receiver architecture covering 54-864 MHz and suitable for tolerating large interferers is presented in 0.18 μm CMOS. It alleviates the problem of LO harmonics mixing with the aid of a heterodyne conversion, and by employing an active feedback, provides an IIP3 of better than +13.4 dBm, comparable with state-of-the-art. Noise canceling techniques are used to improve the NF of the receiver so that the receiver achieves NF of 8.6 and 18 dB in the absence, and presence of an interferer, as strong as 0 dBm, respectively.

A 1.6GHz/4.8GHz dual-band CMOS fractional-N frequency synthesizer for S-Band radio applications

A 1.6 GHz/ 4.8 GHz fractional-N frequency synthesizer in 0.18-μm CMOS technology is presented in this paper. Its purpose is to generate the local oscillator (LO) signals for a fully integrated S-Band transceiver with a direct-conversion receiver (RX) and a dual up-conversion transmitter (TX) to avoid the frequency pulling problem. The synthesizer achieves phase noise of -141.3 dBc/Hz at 1.62 GHz and -132.6 dBc/Hz at 4.86 GHz (both at 3 MHz offset), with reference spurs <;-70.2 dBc for the lower band (LB) and <;-63.8 dBc for the higher band (HB). Total power consumption is 18.2-22.7 mW from a 1 V supply for the VCO and 1.8V for the other synthesizer blocks.