Håkan Olsson
Royal Institute of Technology
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Publication
Featured researches published by Håkan Olsson.
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing | 2003
Yue Wu; Xiaohui Ding; Mohammed Ismail; Håkan Olsson
In this paper, a second-order RF bandpass filter based on active inductor has been implemented in a 0.35 /spl mu/m CMOS process. Issues related to the intrinsic quality factor and dynamic range of the CMOS active inductor are addressed. Tuned at 900 MHz with Q=40, the filter has 28-dB spurious-free-dynamic-range (SFDR) and total current consumption (including buffer stage) is 17 mA with 2.7-V power supply. Experimental results also show the possibility of using them to build higher order RF filter and voltage-controlled oscillator (VCO).
IEEE Journal of Solid-state Circuits | 2002
Adiseno; Mohammed Ismail; Håkan Olsson
A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in an RF Si-bipolar process with an f/sub T/ of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP/sub 3/ (+15.5-dBm OIP/sub 3/) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA DC current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with -10 to -41-dB S/sub 11/ is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 /spl times/ 0.9 mm/sup 2/. The circuit is suitable for area-efficient multiband multistandard low-IF receivers.
european solid-state circuits conference | 2003
Adiseno; H. Magnusson; Håkan Olsson
A balanced wide-band CMOS LNA with 18-26 dB gain, higher than +1.5 dBm IIP/sub 3/ and +20 dBm IIP/sub 2/, and less than 4.6 dB NF is achieved in the 900-MHz, 1.8-GHz and 2.4GHz-band by applying a dual-loop feedback. Measurement results show that the circuit works from DC to a frequency higher than 2.5 GHz (limited by the frequency range of the balun) with S/sub 11/ better than -15 dB. Simulation results show that the circuit has 15 dB gain and 5 dB NF at 5.2 GHz. The LNA consumes 20 mA from 1.8-V voltage-supply. As the output DC level is low, a stacked double balanced switching mixer on the output completes a front-end circuit for wireless receivers without consuming more current. The circuit is implemented in a 0.18/spl mu/m RF-CMOS technology with a die area of 0.4 /spl times/ 0.34 mm/sup 2/. This circuit is suitable for low-cost multiband multistandard front-end receivers.
european conference on circuit theory and design | 2005
Andreas Kämpe; Håkan Olsson
This paper presents a fully integrated low power and low phase-noise VCO, having a tuning range over one octave (1.2 GHz to 2.5 GHz). The architecture is fully differential and the differential tuning offers a common-mode rejection of 31 dB. The VCO is implemented in a 0.18/spl mu/m CMOS process using a 1.8 V supply. The circuit, including the bias, consumes only 11.6 mW at 1.2 GHz oscillation frequency, the phase-noise is -129 dBc/Hz at 1 MHz frequency offset.
international conference on electronics circuits and systems | 2003
Håkan Magnusson; Håkan Olsson
We have designed a new low voltage differential charge-pump for wideband phase-locked loops (PLL). The charge-pump operates at 500 MHz with a supply voltage of 1 V. The differential output voltage range of the cross-coupled charge-pump is 1.4 V. Improved current matching resulted in reduced reference spur levels at the PLL output. Simulations of a PLL showed spurious levels below -88 dBc. The circuit is implemented in a 0.18/spl mu/m CMOS process.
international symposium on circuits and systems | 2000
Yue Wu; Chunlei Shi; Mohammed Ismail; Håkan Olsson
In this paper, a low noise amplifier suitable for wireless WCDMA systems is designed with AMS 0.35 /spl mu/m CMOS process. A biasing circuit with temperature compensation is presented. The simulation result in Cadence shows that the LNA can achieve 12.7 dB power gain and 1.7 dB noise figure with 7 mW power consumption at 27/spl deg/C. The gain and NF variations over -45/spl deg/C to 85/spl deg/C are less than 0.4 dB and 0.1 dB respectively.
radio frequency integrated circuits symposium | 2005
Håkan Magnusson; Håkan Olsson
This paper presents a multistandard transmitter solution using a new power amplifier (PA) driver operating in the broadcast, mobile, and the 2 GHz and 5 GHz ISM bands. The use of dual-loop feedback in the driver provides a matched output without area consuming matching networks. The circuit size is as small as 0.3 mm/sup 2/ for the used 0.18 /spl mu/m CMOS process, saving about 0.7 mm/sup 2/ silicon area. Measurement results show a gain higher than 7.8 dB with a maximum output power of +4 dBm for all bands and using a supply voltage of 1.8 V.
Analog Integrated Circuits and Signal Processing | 2002
Yue Wu; Chunlei Shi; Xiaohui Ding; Mohammed Ismail; Håkan Olsson
In this paper, a class of CMOS biquadratic filter suitable to work at VHF/RF frequency range is presented. The proposed circuit has a simple structure which is analyzed and designed according to a universal Gm-C biquad filter. Simulation and experimental results show that these filters can work in GHz range and have wide tuning range.
IEEE Transactions on Circuits and Systems Ii-express Briefs | 2009
Fredrik Jonsson; Håkan Olsson
A frequency synthesizer targeting low-power packet-based frequency-shift-keying (FSK) applications using open-loop modulation of the oscillator is presented. Unlike conventional implementations, the proposed synthesizer is open both when transmitting and receiving data. It is, therefore, possible to use a wide loop-filter bandwidth without violating the noise or spurious requirements. A wideband loop-filter can be implemented using small component values, allowing an on-chip loop filter. To handle the frequency drift associated with open-loop implementations, a low-leakage charge pump is proposed. The synthesizer is implemented using a 0.18-mum CMOS process. The total power consumption is 9 mW, and the circuit area including the voltage-controlled oscillator (VCO) inductors and on-chip loop-filter is 0.32 mm2. The measured frequency drift indicates a leakage current of below 2 fA.
international conference on electronics, circuits, and systems | 2008
Jian Chen; Fredrik Jonsson; Håkan Olsson; Li-Rong Zheng; Dian Zhou
A novel LC-tank oscillator, where bias noise is decoupled and drain current is shaped in order to reduce phase noise, is presented. Active devices work in a class-C manner, the drain current is pulse shaped and peaks when the oscillator is insensitive to perturbations. Based on the ISF theory, this current shape can improve phase noise performance. Closed-form 1/f2 phase noise equations are derived and compared with those of the classic LC-tank oscillator with the same bias and LC-tank. Simulations agree with conclusions from the theory and show 5.5 dB improvement in 1/f2 phase noise at 1-MHz offset.