Hakaru Tamukoh

Self-organizing map hardware accelerator system and its application to realtime image enlargement

We propose a new fast learning algorithm for SOM and its digital hardware design based on the massively parallel architecture. When this proposed algorithm is realized by using Xilinx XC2V6000-6 FPGA, a maximum performance of 17500 MCUPS is achieved and up to 256 competing units (16 /spl times/ 16 map) can be implemented. Each competing unit have a weight vector which is represented by 128 elements of 16 bits accuracy. Furthermore, we applied the proposed hardware to a realtime digital image enlargement system. In the case of full color (24 bits) image enlargement from QQVGA (160 /spl times/ 120 pixel) to QVGA (320 /spl times/ 240 pixel), a proposed hardware requires only 0.12 second per image, while the personal computer (Intel XEON, 2.8 GHz Dual) requires more than 5 seconds per image.

A bit-shifting-based fuzzy inference for self-organizing relationship (SOR) network

We propose a bit-shifting-based fuzzy inference method for an efficient digital hardware implementation. The proposed fuzzy inference method includes two new techniques which are a membership function generating method and a fast defuzzification method using only “active units”. These techniques reduce a hardware cost and a calculation cost for the membership function and the defuzzification, respectively. In this paper, we apply the proposed method to an execution mode of self-organizing relationship network. Simulation results show that the proposed method has a good approximation ability of a nonlinear I/O relationship as well as the ordinary method.

Parameterized digital hardware design of pulse-coupled phase oscillator networks

This paper proposes a parameterized digital hardware design of pulse-coupled phase oscillator networks that exhibit various synchronization phenomena. We introduce a discretization model with three-valued coupled functions to construct simplified pulse-coupled phase oscillators for parameterized design. The designed digital phase oscillator circuit can change the calculation accuracy and the coupling function shape of oscillators by parameters. One- and two-dimensional pulse-coupled phase oscillator networks are emulated using the designed phase oscillators by setting parameters for the desired network. Experimental results show that the proposed circuit emulates in-/anti-phase and different (out-of-phase) synchronization in two pulse-coupled phase oscillators effectively in an analog large scale integration implementation, and also various synchronization phenomena are observed in large-scale one- and two-dimensional networks.

A digital hardware architecture of self-oganizing rlationship (SOR) ntwork

This paper describes a new algorithm of self-organizing relationship (SOR) network for an efficient digital hardware implementation and also presents its digital hardware architecture. In SOR network, the weighted average of fuzzy inference takes heavy calculation cost. To cope with this problem, we propose a fast calculation algorithm for the weighted average using only active units. We also propose a new generating technique of membership function by representing its width on power-of-two, which suits well with the digital hardware bit-shift process. The proposed algorithm is implemented on FPGA with massively parallel architecture. The experimental result shows that the proposed SOR network architecture has a good approximation ability of nonlinear functions.

FPGA Implementation of Autoencoders Having Shared Synapse Architecture

Deep neural networks (DNNs) are a state-of-the-art processing model in the field of machine learning. Implementation of DNNs into embedded systems is required to realize artificial intelligence on robots and automobiles. Embedded systems demand great processing speed and low power consumption, and DNNs require considerable processing resources. A field-programmable gate array (FPGA) is one of the most suitable devices for embedded systems because of their low power consumption, high speed processing, and reconfigurability. Autoencoders (AEs) are key parts of DNNs and comprise an input, a hidden, and an output layer. In this paper, we propose a novel hardware implementation of AEs having shared synapse architecture. In the proposed architecture, the value of each weight is shared in two interlayers between input-hidden layer and hidden-output layer. This architecture saves the limited resources of an FPGA, allowing a reduction of the synapse modules by half. Experimental results show that the proposed design can reconstruct input data and be stacked. Compared with the related works, the proposed design is register transfer level description, synthesizable, and estimated to decrease total processing time.

A CMOS Unit Circuit Using Subthreshold Operation of MOSFETs for Chaotic Boltzmann Machines

Boltzmann machines are a useful model for deep neural networks in artificial intelligence, but in their software or hardware implementation, they require random number generation for stochastic operation, which consumes considerable computational resources and power. Chaotic Boltzmann machines (CBMs) have been proposed as a model using chaotic dynamics instead of stochastic operation. They require no random number generation, and are suitable for analog VLSI implementation. In this paper, we describe software simulation results for CBM operation, and propose a CMOS circuit of CBMs using the subthreshold operation of MOSFETs.

A Color Quantization Based on Vector Error Diffusion and Particle Swarm Optimization Considering Human Visibility

In this paper, we propose a new color quantization method for generation of the color-reduced images. The proposed method employs a vector error diffusion VED method and a particle swarm optimization PSO. VED method based on Floyd-Steinberg dithering is used for display of the color-reduced image. Furthermore, a color palette used in VED method is optimized by PSO. PSO generates the effective color palette with evaluating a human visibility of the color-reduced image on the display. The validity and the effectiveness of the proposed method are confirmed by some experiments.

Parameterized Digital Hardware Design of Pulse-Coupled Phase Oscillator Model toward Spike-Based Computing

This paper proposes a parameterized digital circuit design approach for pulse-coupled phase oscillators. Our approach aims to construct a reconfigurable hardware platform that emulates a large-scaled pulse-coupled network with complicated interconnection toward spike-based computing. The network, which is described by the parameterized Verilog-HDL, can change the calculation accuracy, the coupling function shape of oscillators, the network size and interaction between oscillators by parameters. Experimental results show that a prototype designed by the proposed approach emulates well in-/anti-phase and different (out-of-phase) synchronization.

Effective and Adaptive Learning Based on Diversive/Specific Curiosity

In this paper, an effective and adaptive learning model, in which a concept of curiosity is used, is proposed. The key idea of the proposed method is to introduce the diversive curiosity in addition to specific curiosity. Furthermore we employ the concept of threshold, which control timing of switching two curiosity modes. By employing two curiosity and making a proper selection of them, a learning ability and adaptability is improved. The effectiveness of the proposed method is verified by some simulations.

Rough-winner-take-all self-organizing neural network for hardware oriented vector quantization algorithm

In this paper, we propose a new vector quantization method for an efficient digital hardware implementation. The basic algorithm of the proposed method is similar to K-means clustering which is the simplest vector quantization. The only different point is that the proposed method employs a rough-winner-take-all as the substitute of ordinary winner-take-all. The simulation results show that quantization performance of the proposed method is nearly equal to neural gas which is an excellent vector quantization. Besides, the proposed method features low hardware complexity as compared to neural gas.