Hamed F. Dadgour

Modeling and analysis of grain-orientation effects in emerging metal-gate devices and implications for SRAM reliability

This work introduces an analytical approach to model the random threshold voltage (Vth) fluctuations in emerging high-k/metal-gate devices caused by the dependency of metal work-function (WF) on its grain orientations. It is shown that such variations can be modeled by a multi-nomial distribution where the key parameters of its probability distribution function (pdf) can be calculated in terms of the physical dimensions of the devices and properties of the materials. It is highlighted for the first time that such variations can have significant implications for the performance and reliability of minimum sized circuits such as SRAM cells.

Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation

This paper highlights and experimentally verifies a new source of random threshold-voltage (V_th) fluctuation in emerging metal-gate transistors and proposes a statistical framework to investigate its device and circuit-level implications. The new source of variability, christened work-function (WF) variation (WFV), is caused by the dependence of metal WF on the orientation of its grains. The experimentally measured data reported in this paper confirm the existence of such variations in both planar and nonplanar high-k metal-gate transistors. As a result of WFV, the WFs of metal gates are statistical distributions instead of deterministic values. In this paper, the key parameters of such WF distributions are analytically modeled by identifying the physical dimensions of the devices and properties of materials used in the fabrication. It is shown that WFV can be modeled by a multinomial distribution where the key parameters of its probability distribution function can be calculated in terms of the aforementioned parameters. The analysis reveals that WFV will contribute a key source of V_th variability in emerging generations of metal-gate devices. Using the proposed framework, one can investigate the implications of WFV for process, device, and circuit design, which are discussed in Part II.

A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates

Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise margin compared to that of standard CMOS gates. Traditionally, this issue has been resolved by employing a pMOS keeper circuit that compensates for leakage current of the pull-down nMOS network. In the earlier technology nodes, the keeper circuit could improve reliability of the dynamic gates with minor performance penalty. However, aggressive scaling trends of CMOS technology along with increasing levels of process variations have reduced effectiveness of the traditional keeper approach. This is because to maintain an acceptable noise margin level in deep sub-100 nm technologies, large pMOS keepers must be employed, which generates substantial contention between the keeper and the pull-down network, and hence results in severe loss of performance and high power consumption. This problem is more severe in wide fan-in dynamic gates due to the large number of leaky nMOS devices connected to the dynamic node. In this paper, a novel variation-tolerant keeper architecture is proposed, which is capable of significantly reducing contention and improving performance and power consumption. Using circuit simulations, the overall improved characteristics of the proposed keeper are demonstrated in comparison to those of the traditional as well as several state-of-the-art keepers. The proposed keeper exhibits the lowest delay deviation under different levels of process variations. Also, it is shown that for an eight-input or gate, in presence of 15% Vth fluctuations, the proposed architecture can lead to 20%, 15%, and more than 40% reduction in power consumption, mean delay, and standard deviation of delay, respectively, when compared to the traditional keeper circuit.

Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design

This paper investigates the process, device, and circuit design implications of grain-orientation-induced work function variation (WFV) in high-k/metal-gate devices. WFV is caused by the dependence of the work function of metal grains on their orientations and is analytically modeled in the companion paper (part I). Using this modeling framework, various implications of WFV are investigated in this paper. It is shown that process designers can utilize the proposed models to reduce the impact of WFV by identifying proper materials and fabrication processes. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS devices and WN and MoN for PMOS devices) are studied, and it is shown that TiN and WN result in lower V_th fluctuations. Moreover, device engineers can study the impact of WFV on various types of classical and nonclassical metal-gate CMOS transistors using these analytical models. As an example, it is shown that, for a given channel length, single-fin FinFETs are less affected by WFV compared to fully depleted SOI and bulk-Si devices due to their larger gate area. Furthermore, circuit designers can benefit from the proposed modeling framework that allows straightforward evaluation of the key performance and reliability parameters of the circuits under such V_th fluctuations. For instance, an SRAM cell is analyzed in the presence of V_th fluctuations due to WFV, and it is shown that such variations can result in considerable performance and reliability degradation.

Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design

For the first time, a new source of random threshold voltage (Vth) fluctuation in emerging metal-gate transistors is identified, analytically modeled and investigated for its device and circuit-level implications. The new source of variability, christened work-function variation (WFV), is caused by the dependency of metal work-function on the orientation of its grains. A statistical framework is developed, which enables estimation of the key parameters of work-function distribution by identifying the physical dimensions of the devices and properties of materials used in the fabrication. This paper offers three major contributions for process, device and circuit designers. First, the proposed model can be employed to identify suitable materials and fabrication processes that can reduce the impact of Vth fluctuation due to WFV. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS and WN and MoN for PMOS devices) are studied and it is shown that TiN and WN result in lower Vth fluctuation. Second, device engineers can benefit from the result of this work by evaluating the WFV level of various types of classical or non-classical metal-gate CMOS transistors. As an example, it is shown that FinFET transistors are less affected by WFV compared to FD-SOI and bulk-Si devices due to their larger gate area. Third, circuit designers can utilize this model to investigate the impact of such a variation on the key performance and reliability parameters of the circuits. For instance, an SRAM cell is analyzed in the presence of Vth fluctuations due to WFV and it is shown that such variations can result in considerable performance and reliability degradation.

Design and analysis of hybrid NEMS-CMOS circuits for ultra low-power applications

Integration of nano-electro-mechanical switches (NEMS) with CMOS technology has been proposed to exploit both near zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, co- design of hybrid NEMS-CMOS as low power dynamic OR gates, SRAM cells, and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60-80% lower switching power and almost zero leakage power consumption with minor delay penalty. However, the hybrid gate outperforms its CMOS counterpart both in terms of delay and switching power consumption with increase in fan-in beyond 12. Additionally, it is shown that the proposed hybrid SRAM cell can achieve almost 8times lower standby leakage power consumption with only minor noise margin and latency cost. Finally, application of NEMS devices as sleep transistors results in upto three orders of magnitude lower OFF current with negligible performance degradation as compared to CMOS sleep switches.

A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution Under Parameter Variations

This paper presents a novel framework for accurate estimation of key statistical parameters of the subthreshold-and gate-leakage distributions of a chip under parameter variations while considering both within-die and die-to-die variabilities in process (P), temperature (T), and supply voltage (V). For the first time, temperature variations and, more importantly, electrothermal couplings between junction (substrate or die) temperature and leakage power have been accounted for in a full-chip leakage estimation methodology. In the proposed framework, instead of exact leakage distribution profile, its statistically important parameters, such as nominal value and spread, are computed. Initially, at the transistor level, a quantitative analysis of the relative sensitivities of device leakage components to P-T-V variations is performed to extract a transistor-level variation model. It is shown that the proposed statistical model, as compared to others in the literature, shows better agreement with BSIM1 model-based simulations. It is also demonstrated that failing to account for temperature variations and electrothermal couplings can result in significant inaccuracy in chip-level leakage estimation. Furthermore, the full-chip leakage-power distribution is used to estimate the leakage-constrained yield under the impact of variations. The calculations show that yield is significantly lowered due to the within-die and die-to-die process and temperature variations. Subsequently, the proposed framework is applied in the leakage estimation of complex logic circuits with a consideration of spatial correlations of process parameters and transistor stacking effects.

Hybrid NEMS-CMOS integrated circuits: A novel strategy for energy-efficient designs

Substantial increase in gate and sub-threshold leakage of complementary metal-oxide-semiconductor (CMOS) devices is making it extremely challenging to achieve energy-efficient designs while continuing their scaling at the same pace as in the past few decades. Designers constantly sacrifice higher levels of performance to limit the ever-increasing leakage power consumption. One possible solution to tackle the leakage issue, which is proposed in this work, is to integrate nano-electro-mechanical switches (NEMS) with CMOS technology. Hybrid NEMS-CMOS technology takes advantage of both near-zero-leakage characteristics of NEMS devices along with high ON current of CMOS transistors. The feasibility of integration of NEMS switches into a CMOS process is illustrated by a practical process flow. Moreover, co-design of hybrid NEMS-CMOS as low-power dynamic OR gates, static random access memory (SRAM) cells and sleep transistors is explored. Simulation results indicate that such hybrid dynamic OR gates can achieve 60-80- lower switching power and almost zero-leakage power consumption with minor delay penalty. However, the hybrid OR gate outperforms its CMOS counterpart both in terms of delay and switching power consumption with increase in fan-in beyond 12. Additionally, it is shown that a hybrid NEMS-CMOS SRAM cell can achieve almost 8- lower standby leakage power consumption with only minor noise margin and latency cost. Finally, application of NEMS devices as sleep transistors results in up to three orders of magnitude lower OFF current with negligible performance degradation as compared to CMOS sleep switches.

Design Optimization of FinFET Domino Logic Considering the Width Quantization Property

Design optimization of FinFET domino logic is particularly challenging due to the unique width quantization property of FinFET devices. Since the keeper device in domino logic is sized based on the leakage current of the pull-down network (PDN) (to meet the noise margin constraint), a reliable statistical framework is required to accurately estimate the domino gate leakage current. Considering the width quantization property, this paper presents such a statistical framework, which provides a reliable design window for keeper sizing to meet the noise margin constraint (for the practical range of threshold voltage variation in sub-32-nm technology nodes). On the other hand, the width quantization property restricts the design optimization (including power/performance characteristics) typically achieved via continuous keeper sizing in planar-CMOS domino logic designs. To cope with this restriction, this paper also introduces a novel methodology for FinFET-based keeper design, which exploits the exclusive property of FinFET devices (capacitive coupling between the front gate and the back gate in a four-terminal FinFET) to simultaneously achieve higher performance and lower power consumption. Using this new methodology, the keeper device is made weaker at the beginning of the evaluation phase to reduce its contention with the PDN, but gradually becomes stronger to provide a higher noise margin.

Scaling and variability analysis of CNT-based NEMS devices and circuits with implications for process design

This work presents an extensive scaling analysis of carbon nanotube (CNT) based Nano-Electro Mechanical Switches (NEMS) considering the effect of process variations on both device and circuit level metrics. Implications for NEMS- material, switch architecture and geometry are also analyzed in detail. A rigorous nano-electromechanical simulation methodology in employed to study the operation and reliability of CNT-NEMS devices. It is shown that CNT-NEMS structures become increasingly susceptible to stiction failure and violating performance requirements as feature size scales down, thereby highlighting the need for advanced nanofabrication techniques if these structures are to be integrated in digital ICs.