Hamid Mehrvar

Hybrid photonic Ethernet switch for datacenters

We demonstrate a photonic packet switch using a hybrid photonics-electronic approach. It uses compression, scrambling and packet size discrimination to allow for the photonic switching of native Ethernet frames.

Scalable photonic packet switch test-bed for datacenters

We demonstrate scaling photonic switch for a datacenter using arrays of fast silicon photonic space switches that are time-slot synchronized, despite the varying distance of interconnected nodes. A low latency scheduling algorithm allows high throughput, with latency comparable to electronic switches.

High-performance silicon photonic tri-state switch based on balanced nested Mach-Zehnder interferometer

AbsatrctThis work proposes a novel silicon photonic tri-state (cross/bar/blocking) switch, featuring high-speed switching, broadband operation, and crosstalk-free performance. The switch is designed based on a 2 × 2 balanced nested Mach-Zehnder interferometer structure with carrier injection phase tuning. As compared to silicon photonic dual-state (cross/bar) switches based on Mach-Zehnder interferometers with carrier injection phase tuning, the proposed switch not only has better performance in cross/bar switching but also provides an extra blocking state. The unique blocking state has a great advantage in applications of N × N switch fabrics, where idle switching elements in the fabrics can be configured to the blocking state for crosstalk suppression. According to our numerical experiments on a fully loaded 8 × 8 dilated Banyan switch fabric, the worst output crosstalk of the 8 × 8 switch can be dramatically suppressed by more than 50 dB, by assigning the blocking state to idle switching elements in the fabric. The results of this work can extend the functionality of silicon photonic switches and significantly improve the performance of on-chip N × N photonic switching technologies.

Photonic Switching of Native Ethernet Frames for Data Centers

We show new techniques of compression, scrambling, and packet size discrimination to implement a photonic-electronic hybrid switch that handle native Ethernet frames. The photonic switch is designed for a silicon photonic switch core.

Scalable architecture and low-latency scheduling schemes for next generation photonic datacenters

Photonic packet switches potentially provide high switching capacity for next-generation datacenters at low cost, low power, and low footprint. In this paper, we address the scalability and packet scheduling for intra-connectivity of next generation photonic datacenters. We first propose a scalable photonic packet fabric based on a stack of small buffer-less silicon photonic switches which are timeslot synchronized by a central controller. We introduce a photonic fabric interface which offers both data path connectivity to the photonic fabric and control path connectivity to the controller. Then, we present centralized scheduling and control methods for photonic packet switching. Our scheduling methods are low complexity iterative algorithms equipped with starvation avoidance capability to meet the latency requirement for packet transmission through the photonic fabric. Simulation results indicate that our scalable scheduling schemes are capable of controlling average and maximum end-to-end packet delay for intra-connectivity in next generation datacenters which are based on buffer-less photonic switching fabrics.

Increasing Capacity of Silicon Photonic Mach-Zehnder Switch Chips for Optical Networks and Datacenters

Silicon photonic switch fabrics require low-loss and low-crosstalk scalable topologies, and optimized photonic components. We analyze the optical performance of switch matrices constructed of Mach-Zehnder cells for a DWDM network circuit switch and for a datacenter packet switch.

Hybrid OPS/EPS Photonic Ethernet Switch and Pure Photonic Packet Switch

We first discuss a hybrid photonics-electronics approach in which large Ethernet packets are switched using a photonic switch and smaller ones are switched using an electronic packet switch. It uses compression and scrambling to allow error-free photonic switching of native Ethernet frames. The issues associated with the splitting of packets of a flow into two streams of short and long packets for switching through electronic and photonic switches, respectively, are packet reordering and contention control.

Silicon Photonic Switch Subsystem With 900 Monolithically Integrated Calibration Photodiodes and 64-Fiber Package

Monolithic germanium photodiodes on every cell calibrate a 32×32 silicon photonic switch of 448 Mach-Zehnders in 10 minutes. 64 fibers permanently attached through a waveguide concentrator in a wire-bonded BGA achieve 2.9dB C-band TE fiber-to-die.

Loss and crosstalk solutions in fast silicon photonic switch systems

Silicon photonic carrier-injection switches can enable Petabits/s packet switch cores. These switches are compatible with 100GigE and future 400GigE link budgets, using a crosstalk suppression topology, aggressive loss reduction including 0.001dB crossings, polarization control and rapid auto-calibration, and by removing self-heating transients to prevent dynamic crosstalk.

Design implications of the add/drop ratio in transparent photonic networks

Using the Engset traffic model, we demonstrate conflicting effects of add/drop ratio on performance of the access networks and that of the core networks. This will have important design implications to future transparent photonic networks.