Hamid Reza Naji

An efficient crossover architecture for hardware parallel implementation of genetic algorithm

In this article a new architecture for hardware implementation of genetic algorithm in reconfigurable embedded systems is presented. The main idea is based on the efficient use of a genetic algorithms crossover operator to enhance the speed of algorithm to reach an optimal solution. In this article a new crossover called DSO and also two new architectures for implementation of crossover operators are introduced to provide suitable solutions for solving the problems related to fitness function of the genetic algorithm. At first, some optimum operators are selected and then utilized in a new parallel architecture to increase the speed and accuracy of algorithm convergence. Finally, based on reusability of existing resources, the main idea of the article is introduced to improve the performance of the algorithm and finding the optimal solution. The properties of FPGAs such as flexibility and parallelism help this purpose.

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

The threshold voltage drifts induced by positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) weaken nMOS and pMOS, respectively. These long-term aging threshold voltage drifts degrade SRAM cell stability, margin, and performance. This paper presents a low area overhead adaptive body bias (ABB) circuit that compensates BTI aging effects and also improves performance of an aged SRAM cell. The proposed circuit uses a control circuit and word line voltage to control the voltage applied to the body of 6T SRAM cells transistors such that the BTI effect dependence of threshold voltage is reduced. In the worst case, the proposed ABB reduces the HOLD SNM degradation by 6.85%, the READ SNM degradation by 12.24%, the WRITE margin degradation by 2.16%, the READ delay by 28.68%, and the WRITE delay by 32.61% compared to the conventional SRAM cell at 108 s aging time.

An energy efficient multi-level route-aware clustering algorithm for wireless sensor networks

Propose a new clustering and route construction algorithm. Implement a route conscious method in which nodes could gain desired information about possible routes to the destination and construct an optimal routing tree with the least transmission cost.Save energy with decreasing the number of control packets.Balance intra-cluster and inter-cluster energy consumption among CHs, prevent the premature death of CHs near the BS.Define new criteria in route specification and cluster formation stages, assign an effective weight to each variable based on energy efficiency requirements, improves nodes longevity and prolong the network lifetime. Energy maintenance is one of the crucial characteristics for wireless sensor networks. Clustering techniques in WSNs is wildly used to cope with sensor network deficiencies. Organizing nodes in such clusters and specifying a particular node in each cluster to undertake the task of intra-cluster and inter-cluster data communications leads to alleviate the number of transmissions and hence longer lifetime of the Network. Most of decentralized clustering protocols are performed without any acknowledgement of a route which data traverse to reach the base station. In this paper, a new distributed energy efficient multi-level route-aware clustering algorithm for WSNs called MLRC is proposed. To establish tree among sensor nodes, MLRC applies a route conscious manner in which nodes could gain desired information about possible routes to the destination. The proposed protocol eliminates extra generation of routing control packets by implementing cluster formation and routing tree construction, concurrently. Cluster heads are elected based on effective parameters. The algorithm could moderate energy consumption of relays close to the base station with assigning probability to adjacent cluster head and avoiding the insistence on the nearest cluster head selection. Experimental results illustrate that the protocol improves network longevity in comparison with other known protocols. Display Omitted

New SRAM design using body bias technique for low-power and high-speed applications

In this paper, a new SRAM cell with body-bias actively controlled by a control circuit and word line is introduced to realize low-power and high-speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cells transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade-off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%. Copyright

Improving HBQ Authentication and Access control in wireless sensor network

Wireless sensor networking continues to evolve as one of the most exciting and challenging research areas of our time. In the real world, there are many applications of wireless sensor networks that collect and send sensitive important information to the Base Station. Due to the wireless communications insecure nature and considering the fact that sensor nodes always are distributed in a hostile environment, having well implemented security scheme is very essential. Considering important security services like Authentication and Access control, we proposed a new security scheme for these networks. In the proposed scheme, Bloom Filter data structure has been used for pre-Authentication and Access controls; also for main Authentication service the Elliptic Curve Diffie-Hellman scheme has been implemented. The implementation results show that our scheme has significant improvement comparing to HBQ scheme regarding power and time consumption.

Providing QoS guarantee of timeliness in wireless sensor networks with a new routing methodology

Wide spread use of wireless sensor networks (WSNs) in critical applications shows the importance of Quality of service (QoS) in these networks. Timeliness is one of the QoS parameters which has great importance in real time applications such as earthquake detection. Several geographic routing protocols have been proposed for WSNs which provide QoS support in timeliness domain. Most of these protocols use one-hop neighborhood information to make routing decisions. Timeliness can be improved by using multi-hop neighborhood information which increases control overhead and decreases network lifetime. In other words, the choice of two-hop neighborhood information is a tradeoff between timeliness and control overhead. In this paper, we propose a QoS-aware routing protocol, called Maximum Speed Routing Protocol (MSRP) for WSNs to provide QoS-guarantee in timeliness domain. MSRP is based on two-hop neighborhood information with low control overhead and it can improve timeliness by sending packets with maximum speed across the network. Also, MSRP considers the distance between a neighbor and destination to determine next forwarding node and uses a different method to estimate delay between two neighbors. Simulation results show that MSRP improves performance in terms of end-to-end delay, delivery ratio and hop counts.

A CNFET-based hybrid multi-threshold 1-bit full adder design for energy efficient low power applications

ABSTRACT In this article, a low-power and energy-efficient hybrid full adder circuit is proposed, which is implemented based on multi-threshold NAND and NOR gates and transmission gate multiplexers. In order to implement this circuit, carbon nano tube field effect transistors are utilised. For evaluating the proposed design, comprehensive simulations are performed with regard to the most important aspects power, delay and power-delay product. The results are presented and displayed the superiority of the proposed cell in different voltage levels, load conditions, temperatures and robustness against process variations.

RTEA: Real-Time and Energy Aware Routing for Industrial Wireless Sensor Networks

This paper proposes a real-time and energy aware routing protocol for industrial wireless sensor networks, called RTEA. Two-hop neighborhood information routing is adopted from THVR routing protocol, however our routing protocol has low control packet overhead and differentiates packets based on their deadlines. The packet deadline is updated in each hop without using globally synchronized clocks. In addition to velocity, the distance to the sink is considered for reducing the number of relaying hops. Also, the delay between two one-hop neighbors is estimated by a new mechanism which considers the time that packets spend in each node beside the link delay. Simulation results show that RTEA can improve the performance in terms of delivery ratio and energy consumption.

A Clustering Algorithm for Communication-Aware Scheduling of Task Graphs on Multi-Core Reconfigurable Systems

In this paper, a clustering algorithm called the Reconfigurable Dominant Sequence Clustering (ReDSC), is proposed. The experiments show that ReDSC reduces the parallel run time efficiently by 30 percent. Moreover, an empirical comparison of ReDSC with its peer in the multi-processor model, i.e., DSC algorithm, is provided and the results demonstrate the 35 percent improvement of ReDSC over DSC. Then, a hardware implementation of a dynamic scheduler for run-time communication-aware scheduling of hardware tasks is proposed. The proposed scheduler makes use of the ReDSC algorithm for allocating tasks to the processing reconfigurable cores, dynamically considering the communication costs. The simulation results illustrate the benefits of the proposed scheduler as compared to that of other static and basic schedulers in the technical literature.

Parallel Massive Data Monitoring and Processing Using Sensor Networks

Sensor Networks have great potential for many applications. In time-critical and security applications, it is important to have on time delivery, minimum access time and maximum data rate. Most of sensor networks have a large number of sensor nodes which considering the memory and processor of each of them all together they provide a huge data storage space and also high processing capability. In this paper we propose a method to implement the parallel data monitoring and processing on a large number of sensor nodes in a sensor network that can be used is a security environment. We can use the sensor, memory and processing elements of each sensor node store and process a part of large database or computation. The data which is entered to the database can come from the sensors of sensor nodes. By this method not only we can use the memory of each sensor node to store apart of our data but also we can do parallel processing on the stored data of all sensor nodes. The results of our simulations show this method provides a huge storage space to store a considerable amount of data and also speed up the computations.