Hamza Issa

High-Q Slow-Wave Coplanar Transmission Lines on 0.35

In this letter, experimental results and trends for shielded coplanar waveguide transmission lines (S-CPW) implemented in a 0.35 μm CMOS technology are provided. Because of the introduction of floating strips below the CPW transmission line, high effective dielectric permittivity and quality factor are obtained. Three different geometries of S-CPW transmission lines are characterized. For the best geometry, the measured effective dielectric permittivity reaches 48, leading to a very high slow-wave factor and high miniaturization. In addition, measurements demonstrate a quality factor ranging from 20 to 40 between 10 and 40 GHz, demonstrating state-of-the-art results for transmission lines realized in a low-cost CMOS standard technology.

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This paper describes a new concept of substrate integrated waveguide (SIW): a slow-wave substrate integrated waveguide (SW-SIW). Compared to a conventional SIW, the proposed topology requires a double-layer substrate with a bottom layer including internal metallized via-holes connected to the bottom conductive plane. The slow-wave effect is obtained by the physical separation of electric and magnetic fields in the structure. Electromagnetic simulations show that this topology of SIW allows decreasing the longitudinal dimension by more than 40% since the phase velocity is significantly smaller than that of a classical SIW. Simultaneously, the lateral dimension of the waveguide is also reduced. By considering a double-layer technology, SW-SIWs exhibiting a cutoff frequency of 9.3 GHz were designed, fabricated, and measured. The transversal dimension and the phase velocity of the proposed SW-SIW are both reduced by 40% as compared to a classical SIW designed for the same cutoff frequency, leading to a significant surface reduction. Moreover, an original kind of taper is proposed to achieve a good return loss when the SW-SIW is fed by a microstrip transmission line.

m CMOS Process

High-performance on-chip coplanar-waveguide (CPW) transmission lines (TLs) were fabricated on locally formed porous silicon membranes on the Si wafer, and their millimeter-wave (mmW) characteristics were measured up to 110 GHz. It was demonstrated that a quality factor three times higher than that of conventional CPWs fabricated in standard CMOS on bulk crystalline Si can be obtained in mmW frequencies. The measured values of the attenuation loss were ~ 0.35 dB/mm at 60 GHz and ~ 0.55 dB/mm at 110 GHz. The obtained attenuation loss was independent of the realized TL characteristic impedance (50 and 145 Ω). These results are better than the state-of-the-art results in the literature obtained using CMOS on high-resistivity (HR) Si substrates (CMOS HR technologies). They show the potential of using locally formed porous Si membranes in mmW shielding on the Si wafer, in addition to the already demonstrated RF shielding (frequencies up to 40 GHz).

Slow-Wave Substrate Integrated Waveguide

This paper presents the general fundamental equations for a miniaturized narrow bandpass DBR filter, where the miniaturization is achieved by loading the transmission lines with capacitors while increasing their characteristic impedance. The derived fundamental equations show the interesting performances of this miniaturized filter when compared with a classical one. Not only high miniaturizing percentage, but also better out-of-band rejection could be achieved. Hybrid classical and miniaturized DBR prototypes with a 1 GHz center frequency, based on a microstrip technology, were fabricated and measured. The obtained results show miniaturization of 75% and better filter out-of-band rejection. The increase of the insertion loss is solved by distributing the capacitance along the stub length.

On-Chip High-Performance Millimeter-Wave Transmission Lines on Locally Grown Porous Silicon Areas

Thick porous Si layers locally formed on a low resistivity Si wafer were studied for their application in on-chip RF device integration. A comparison was made between the above porous Si substrate and trap-rich high resistivity Si (trap-rich HR Si), which constitutes a state-of-the-art substrate for RF integration, by integrating identical co-planar waveguide transmission lines (CPW TLines) on both porous Si layer/low resistivity Si and trap-rich high resistivity Si. It was showed that signal attenuation on the porous Si layer is 30% lower than on trap-rich HR Si. This suggests lower losses or better RF shielding in the case of porous Si. In addition, CPW TLines were designed and realized on porous Si substrate for the frequency range 1-110GHz. The measured attenuation constant at 60 and 110GHz was respectively 0.33 and 0.55 dB/mm. This result competes very well with the best literature results on CMOS integrated transmission lines, even though the metal lines in the case of the porous Si substrate were not optimized.

Miniaturized DBR filter: Formulation and performances improvement

This paper gives a complete theoretical study in a narrow band for the parallel-coupled filters based on short-circuited stub-loaded resonators. It describes a synthesis method for this filter topology, and a complete resonant mode analysis to fully control the spurious frequencies positions. To enlarge the out-of-band rejection, an original technique, based on simple design steps, is used to address tuning of extra transmission zeros. Harmonic was suppressed to better than 35 dB with a wide stopband of more than six time the fundamental frequency. Design equations and design rules are given. Finally, several three-pole bandpass filters are designed and characterized in stripline and miscrostrip technologies to demonstrate the efficiency of the proposed concepts.

Porous Si as a substrate material for RF passive integration

We report on the design, fabrication, and characterization of high-performance stepped-impedance filters (SIFs) on a locally formed porous Si layer on the CMOS Si wafer. This technology provides the appropriate platform to reduce the high losses within the Si substrate, along with the possibility to tune the substrate permittivity in order to achieve high characteristic impedance (ZC) transmission lines, which are important for the specific filters and other passive circuits, e.g., power dividers. By combining high-ZC coplanar waveguides (CPWs) and low-ZC slow-wave CPWs (S-CPWs), high-quality SIFs were achieved, with cutoff frequencies at 30 and 60 GHz. These SIFs were characterized in the frequency range of 0-100 GHz and demonstrated an insertion loss lower than 2 dB in the whole passband and a rejection higher than 30 dB in the stopband. The achieved performance is better than that exhibited by SIFs using only S-CPWs.

Full Study of the Parallel-Coupled Stub-Loaded Resonator: Synthesis Method in a Narrow Band With an Extended Optimal Rejection Bandwidth

This paper describes a synthesis method for parallel-coupled filters based on short-circuited stub-loaded resonators. Synthesis formulas were derived for homogeneous medium. Simulations are presented to validate the theory for three relative bandwidths 2, 4 and 8 %. For a proof-of-concept a third-order stripline bandpass filter was designed with a passband ripple of 0.01 dB and a relative bandwidth of 4.5%. Theory, simulations and measurements are in good agreement and thus validate the theory.

High-Performance On-Chip Low-Pass Filters Using CPW and Slow-Wave-CPW Transmission Lines on Porous Silicon

A new miniature Dual Behavior Resonator (DBR) topology with capacitors placed in series between the feed lines and the stubs is demonstrated. Design equations are derived. For a proof-of-concept, a first-order prototype with a 1-GHz working frequency and 70 % size reduction is realized, measured and compared to a classical DBR. The design method is simpler and more accurate compared to a miniaturized DBR with capacitors connected at the end of the stubs. Hence, the agreement between simulation and measurement results is better than previously published results of a miniature DBR using capacitors at the end of the stubs. Results also point out a quality factor improvement of 12 %.

Synthesis method for the parallel-coupled stub-loaded resonator filters

This paper presents a new application for Slow-wave Microstrip (SMS) technique in miniaturization of rectangular patch antennas. The designed patches resonate around the Industrial Scientific and Medical (ISM) radio bands, 2.45 GHz, and were optimized using HFSS. The SMS design technology used is based on the insertion of via holes within multilayer substrate. The simulation results show that the patch area is reduced up to 32% while keeping an acceptable antenna gain (6.22dB) and unmodified other electrical characteristics.