Han-Gu Kim

Novel ESD strategy for high voltage non-volatile programming pin application

This paper presents a novel ESD strategy for non-volatile memory (NVM) programming pin in a 0.13um/30V technology. Suggested scheme can provide not only a major current discharge path to protect the internal circuit from ESD damage but also a voltage clamping function to prevent the soft error of programmed data during the ESD event. It has been validated by TLP experiments and TCAD simulation.

A new high-voltage tolerant I/O for improving ESD robustness

Abstract A new design scheme to improve the ESD performance of high voltage tolerance (HVT) I/O is presented in this paper. Without calling for the additional process steps or modification, the proposed design enhances the ESD failure immunity by having both of the stacked nMOS transistors turned on simultaneously. The ESD characteristic of new HVT IO structure has been measured using TLP and shows the improvement in It2 to 2.2A from 0.5 A and Vt1 to 6.1 V from 11.5 V, respectively.