Han Weihua

Design, fabrication and characterization of a high-performance microring resonator in silicon-on-insulator

A high-performance microring resonator in a silicon-on-insulator rib waveguide is realized by using the electron beam lithography followed by inductively coupled plasma etching. The design and the experimental realization of this device are presented in detail. In addition to improving relevant processes to minimize propagation loss, the coupling efficiency between the ring and the bus is carefully chosen to approach a critical coupling for high performance operating. We have measured a quality factor of 21,200 and an extinction ratio of 12.5dB at a resonant wavelength of 1549.32nm. Meanwhile, a low propagation loss of 0.89dB/mm in a curved waveguide with a bending radius of 40/?m is demonstrated as well.

Quantum transport characteristics in single and multiple N-channel junctionless nanowire transistors at low temperatures

Single and multiple n-channel junctionless nanowire transistors (JNTs) are fabricated and experimentally investigated at variable temperatures. Clear current oscillations caused by the quantum-confinement effect are observed in the curve of drain current versus gate voltage acquired at low temperatures (10 K–100 K) and variable drain bias voltages (10 mV–90 mV). Transfer characteristics exhibit current oscillation peaks below flat-band voltage (VFB) at temperatures up to 75 K, which is possibly due to Coulomb-blocking from quantum dots, which are randomly formed by ionized dopants in the just opened n-type one-dimensional (1D) channel of silicon nanowires. However, at higher voltages than VFB, regular current steps are observed in single-channel JNTs, which corresponds to the fully populated subbands in the 1D channel. The subband energy spacing extracted from transconductance peaks accords well with theoretical predication. However, in multiple-channel JNT, only tiny oscillation peaks of the drain current are observed due to the combination of the drain current from multiple channels with quantum-confinement effects.

An efficient dose-compensation method for proximity effect correction

A novel simple dose-compensation method is developed for proximity effect correction in electron-beam lithography. The sizes of exposed patterns depend on dose factors while other exposure parameters (including accelerate voltage, resist thickness, exposing step size, substrate material, and so on) remain constant. This method is based on two reasonable assumptions in the evaluation of the compensated dose factor: one is that the relation between dose factors and circle-diameters is linear in the range under consideration; the other is that the compensated dose factor is only affected by the nearest neighbors for simplicity. Four-layer-hexagon photonic crystal structures were fabricated as test patterns to demonstrate this method. Compared to the uncorrected structures, the homogeneity of the corrected hole-size in photonic crystal structures was clearly improved.

Fermi level pinning effects at gate–dielectric interfaces influenced by interface state densities*

The dependences of Fermi-level pinning on interface state densities for the metal–dielectric, ploycrystalline silicon–dielectric, and metal silicide–dielectric interfaces are investigated by calculating their effective work functions and their pinning factors. The Fermi-level pinning factors and effective work functions of the metal–dielectric interface are observed to be more susceptible to the increasing interface state densities, differing significantly from that of the ploycrystalline silicon–dielectric interface and the metal silicide–dielectric interface. The calculation results indicate that metal silicide gates with high-temperature resistance and low resistivity are a more promising choice for the design of gate materials in metal-oxide semiconductor (MOS) technology.

Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm2V−1s−1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si–SiO2 interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.

Reduction of proximity effect in fabricating nanometer-spaced nanopillars by two-step exposure

A two-step exposure method to effectively reduce the proximity effect in fabricating nanometer-spaced nanopillars is presented. In this method, nanopillar patterns on poly-methylmethacrylate (PMMA) were partly cross-linked in the first-step exposure. After development, PMMA between nanopillar patterns was removed, and hence the proximity effect would not take place there in the subsequent exposure. In the second-step exposure, PMMA masks were completely cross-linked to achieve good resistance in inductively coupled plasma etching. Accurate pattern transfer of rows of nanopillars with spacing down to 40 nm was realized on a silicon-on-insulator substrate.