Hana Kubatova

Dependable design technique for system-on-chip

A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters.

Fault tolerant system design method based on self-checking circuits

This paper describes a highly reliable digital circuit design method based on totally self checking blocks implemented in FPGAs. The bases of the self checking blocks are parity predictors. The parity predictor design method based on multiple parity groups is proposed. Proper parity groups are chosen in order to obtain minimal area overhead and to decrease the number of undetectable faults

Dependable Design for FPGA Based on Duplex System and Reconfiguration

A technique for highly reliable digital design in FPGAs is presented. Two FPGAs are used for duplex system design, but better dependability parameters are obtained by combination of totally self checking blocks based on parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained by XILINX FPGA implementation by EDA tools. The dependability model and dependability calculations are presented

Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications

We propose a novel two-level Boolean minimizer coming in succession to our previously developed minimizer BOOM, so we have named it BOOM-II. It is a combination of two minimizers, namely BOOM and FC-Min. Each of these two methods has its own area where it is most efficiently applicable. We have combined these two methods together to be able to solve all kinds of problems efficiently, independently on their size or nature. The tool is very scalable in terms of required runtime and/or quality of the solution. It is applicable to functions with an extremely large number of both input and output variables. The minimization process is very flexible and can be driven by miscellaneous user-defined constraints, such as low-power design, design-for-testability and decomposition constraints. Some of the application areas are described in the paper

Dependability computations for fault-tolerant system based on FPGA

The methods how to design a fault-tolerant system based on FPGAs is presented. The evaluation of the whole design according the computations of reliability and dependability characteristics is described. The formal dependability model and computations obtained on the base of this model is summarized.

FC-Min: a fast multi-output Boolean minimizer

We present a novel heuristic algorithm for two-level Boolean minimization. In contrast to the other approaches, the proposed method firstly finds the coverage of the on-sets and from that it derives the group implicants. No prime implicants of the single functions are being computed; only the necessary implicants needed to cover the on-sets are produced. This reverse approach makes the algorithm extremely fast and minimizes the memory demands. It is most efficient for functions with a large number of output variables, where the other minimization algorithms (e.g. ESPRESSO) are too slow. It is also very efficient for highly unspecified functions, i.e. functions with only few terms defined.

Finite State Machine Implementation in FPGAs

This paper deals with the possibility of the description and decomposition of the finite state machine (FSM). The aim is to obtain better placement of a designed FSM to the selected FPGA. It compares several methods of encoding of the FSM internal states with respect to the space (the number of CLB blocks) and time characteristics. It evaluates the FSM benchmarks and seeks for such qualitative properties to choose the best method for encoding before performing all FOUNDATION CAD system algorithms, since this process is time consuming. The new method for encoding the internal FSM states is presented. All results are verified by experiments.

Dependability Computation for Fault Tolerant Reconfigurable Duplex System

This paper describes a design method for highly reliable digital circuits based on totally self checking blocks implemented in FPGAs. The dependability model and dependability calculations are proposed. The self checking blocks are based on a parity predictor. These blocks are linked together to form a compound design. Our adapted duplex system is used as a basic structure to increase availability parameters and protect system against single even upsets (SEUs). This adapted duplex system is realized by two FPGAs, where each FPGA can be reconfigured when a fault is detected. Availability parameters have been calculated by dependability Markov models

P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers

Software Defined Networking and OpenFlow offer an elegant way to decouple network control plane from data plane. This decoupling has led to great innovation in the control plane, yet the data plane changes come at much slower pace, mainly due to the hard-wired implementation of network switches. The P4 language aims to overcome this obstacle by providing a description of a customized packet processing functionality for configurable switches. That enables a new generation of possibly heterogeneous networking hardware that can be runtime tailored for the needs of particular applications from various domains. In this paper we contribute to the idea of P4 by presenting design, analysis and experimental results of our packet parser generator. The generator converts a parse graph description of P4 to a synthetizable VHDL code suitable for FPGA implementation. Our results show that the generated circuit is able to parse 100 Gbps traffic with fairly complex protocol structure at line rate on a Xilinx Virtex-7 FPGA. The approach can be used not only in switches, but also in other appliances, such as application accelerators and smart NICs. We compare the generated output to a hand-written parser to show that the price for configurability is only a slightly larger and slower circuit.

FPGA based design of the railway's interlocking equipments

This paper describes the architecture of a safety system of the railways interlocking equipment, which has been developed for Czech railways. The system will be used for the railway crossing gate. This system is based on FPGA blocks and has to fulfill the requirements for a fault tolerant system with a fail-safe function. The dual logic and TMR principle are used to increase its dependability. Several self-test and self-diagnostics features are used, such as an LFSR based built-in self-test, the FPGA readback and 1 out of 2 error detection codes. The functional logic uses a majority correction and the FPGA box reprogramming to precede the failure. The reliability analyses, models and reliability characteristics calculations of this system are described. Markov chain models are used for the reliability analyses. The TMR principles for fault tolerant system and the dual-TMR logic have been used in our design and both attempts are compared.