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Dive into the research topics where Hans Boettiger is active.

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Featured researches published by Hans Boettiger.


arXiv: High Energy Physics - Lattice | 2010

QPACE - a QCD parallel computer based on Cell processors

H. Baier; Hans Boettiger; C. Gomez; Dirk Pleiter; Nils Meyer; A. Nobile; Zoltan Fodor; Joerg-Stephan Vogt; K.-H. Sulanke; Simon Heybrock; Frank Winter; U. Fischer; T. Maurer; Thomas Huth; Ibrahim A. Ouda; M. Drochner; Heiko Schick; F. Schifano; A. Schäfer; H. Simma; J. Lauritsen; Norbert Eicker; Marcello Pivanti; Matthias Husken; Thomas Streuer; Gottfried Goldrian; Tilo Wettig; Thomas Lippert; Dieter Hierl; Benjamin Krill

QPACE is a novel parallel computer which has been developed to be primarily used for lattice QCD simulations. The compute power is provided by the IBM PowerXCell 8i processor, an enhanced version of the Cell processor that is used in the Playstation 3. The QPACE nodes are interconnected by a custom, application optimized 3-dimensional torus network implemented on an FPGA. To achieve the very high packaging density of 26 TFlops per rack a new water cooling concept has been developed and successfully realized. In this paper we give an overview of the architecture and highlight some important technical details of the system. Furthermore, we provide initial performance results and report on the installation of 8 QPACE racks providing an aggregate peak performance of 200 TFlops.


Ibm Journal of Research and Development | 2009

IBM BladeCenter QS22: design, performance, and utilization in hybrid computing systems

Jörg-Stephan Vogt; Rudolf Land; Hans Boettiger; Z. Krnjajic; Heinz Baier

The IBM BladeCenter® QS22 is a blade server that is based on two IBM PowerXCell™ 8i processors. This server is the successor of the QS21 server, which delivered excellent multicore Cell Broadband Engine® (Cell/B.E.) performance for workstation, server, and supercomputer customers. The IBM PowerXCell 8i processor represents a second generation of the Cell Broadband Engine Architecture. It significantly improves floating-point performance and allows for larger memory configurations. In this paper, we provide an overview of the architecture and design of this newer QS22 system and explain some of the design decisions. We discuss hardware and application performance, power efficiency, manageability, and configuration options, and how these factors affect hybrid system configurations. Finally, we briefly describe two hybrid system configurations that utilize the QS22 system. One configuration involves the Roadrunner system at Los Alamos National Laboratory, the first one-petaflops supercomputer in the world. The second configuration involves a hybrid system with a PCI Express® switch used for coupling.


arXiv: High Energy Physics - Lattice | 2009

Status of the QPACE Project

H. Baier; Hans Boettiger; Stefan Solbrig; Dirk Pleiter; Nils Meyer; A. Nobile; Zoltan Fodor; K.-H. Sulanke; Simon Heybrock; Frank Winter; U. Fischer; T. Maurer; Thomas Huth; Ibrahim A. Ouda; M. Drochner; Heiko Schick; F. Schifano; H. Simma; J. Lauritsen; Norbert Eicker; Marcello Pivanti; A. Schafer; Thomas Streuer; Gottfried Goldrian; Tilo Wettig; Thomas Lippert; Dieter Hierl; Benjamin Krill; R. Tripiccione; J. McFadden

We give an overview of the QPACE project, which is pursuing the development of a massively parallel, scalable supercomputer for LQCD. The machine is a three-dimensional torus of identical processing nodes, based on the PowerXCell 8i processor. The nodes are connected by an FPGAbased, application-optimized network processor attached to the PowerXCell 8i processor. We present a performance analysis of lattice QCD codes on QPACE and corresponding hardware benchmarks.


Ibm Journal of Research and Development | 2013

Early experiences with scientific applications on the IBM Blue Gene/Q supercomputer

Sadaf R. Alam; Constantine Bekas; Hans Boettiger; Alessandro Curioni; Gilles Fourestey; Willi Homberg; Michael Knobloch; Teodoro Laino; Thilo Maurer; Bernd Mohr; Dirk Pleiter; A. Schiller; Thomas C. Schulthess; Valéry Weber

We report early experiences with porting highly complex scientific applications to the IBM Blue Gene®/Q platform. In addition, we report our progress in porting performance analysis tools that are deemed to be key in helping users understand massively parallel, massively threaded applications. Porting proved to be quite a smooth process. Although in this early study we did not use the full array of the novel architectural features, we nevertheless obtained quite satisfactory, though preliminary, performance results. Thus, we can safely anticipate impressive further improvements in overall performance once the full capability of the Blue Gene/Q architecture is exploited.


ieee international conference on high performance computing, data, and analytics | 2015

Accelerating LBM and LQCD Application Kernels by In-Memory Processing

Paul F. Baumeister; Hans Boettiger; José R. Brunheroto; Thorsten Hater; Thilo Maurer; Andrea Nobile; D. Pleiter

Processing-in-memory architectures promise increased computing performance at decreased costs in energy, as the physical proximity of the compute pipelines to the data store eliminates overheads for data transport. We assess the overall performance impact using a recently introduced architecture of that type, called the Active Memory Cube, for two representative scientific applications. Precise performance results for performance critical kernels are obtained using cycle-accurate simulations. We provide an overall performance estimate using performance models.


european conference on parallel processing | 2016

Exploiting In-Memory Processing Capabilities for Density Functional Theory Applications

Paul F. Baumeister; Thorsten Hater; D. Pleiter; Hans Boettiger; Thilo Maurer; José R. Brunheroto

Processing-in-memory (PIM) is an approach to address the data transport challenge in future HPC architectures and various designs have been explored in the past. Despite, it remains unclear how scientific applications could efficiently exploit massively-parallel HPC architectures integrating PIM modules. In this paper we address this question for material science applications for which we ported relevant kernels to the Active Memory Cube architecture developed by IBM Research.


Archive | 2007

Method for Autonomous Dynamic Voltage and Frequency Scaling of Microprocessors

Peter Altevogt; Hans Boettiger; Wesley M. Felter; Charles R. Lefurgy; Lutz Stiege; Malcolm Scott Ware


Computer Science - Research and Development | 2010

QPACE: power-efficient parallel architecture based on IBM PowerXCell 8i

H. Baier; Hans Boettiger; M. Drochner; N. Eicker; U. Fischer; Zoltan Fodor; Andreas Frommer; C. Gomez; Gottfried Goldrian; Simon Heybrock; Dieter Hierl; Matthias Husken; Thomas Huth; Benjamin Krill; J. Lauritsen; Thomas Lippert; T. Maurer; B. Mendl; Nils Meyer; A. Nobile; I. Ouda; Marcello Pivanti; Dirk Pleiter; Manfred Ries; A. Schäfer; Heiko Schick; F. Schifano; H. Simma; Stefan Solbrig; Thomas Streuer


Archive | 2001

Method for unwinding a program call stack

Graham W. Ewart; Hans Boettiger; Patricia A. Healy; James T. Mulvey; Gregory T. Reid; David J. Sudlik


Archive | 2008

Method for autonomous dynamic voltage and frequency scaling of microprocessors and computer system

Peter Altevogt; Hans Boettiger; Lutz Stiege

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A. Nobile

University of Regensburg

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T. Maurer

University of Regensburg

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Dirk Pleiter

University of Regensburg

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H. Simma

University of Regensburg

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Nils Meyer

University of Regensburg

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Simon Heybrock

University of Regensburg

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Thomas Lippert

Forschungszentrum Jülich

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Thomas Streuer

University of Regensburg

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Zoltan Fodor

University of Wuppertal

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