Hans Boeve

Comparison between patterned and unpatterned electrodeposited spin-valve sensors

Electrodeposited spin-valves on GaAs substrates were patterned down into 80 /spl mu/m, 4 /spl mu/m and 2 /spl mu/m strips. A symmetric spin-valve configuration is used which incorporates an artificially hard substructure. Sensitivities up to 1.5%/Oe were observed, these being the highest ever observed in electrodeposited structures. Upon patterning an increased antiferromagnetic contribution of the inner hard substructure was seen.

Degradation and breakdown of plasma oxidized magnetic tunnel junctions: single trap creation in Al/sub 2/O/sub 3/ tunnel barriers

We present an in-depth analysis of the reliability of plasma oxidized magnetic tunnel junctions, using constant voltage stress until breakdown. In the stress measurements, prebreakdown current jumps were also observed. We show that the prebreakdown jumps, as well as the final breakdown are caused by the generation of single trap conduction paths in the barrier. Finally, we demonstrate that applying stress can also cause gradual resistance changes, which can either be reversible or irreversible.

Technology assessment for MRAM cells with magnet/semiconductor bits

Although MRAM circuits can be fabricated without the need for an integrated semiconductor switch in each bit, most applications will require a DRAM-like floorplan with combined magnetlsemiconductor bits. In a first approach to assess the feasibility of such integration, we have integrated spin-valve structures with semiconductor diodes [I]. Further, in an [MEC I INESC collaboration (ESPRIT #28.229 I TI-MRAM) the integration feasibility of tunnel junctions is assessed. The main issues we are tackling are the fabrication of arrays of magnetic tunneljunction I semiconductor elements and the MTI performance as a function of the parameters of the integration pmcess. In this paper we present results of our assessment of MRAM circuits with magnetlsemiconductor bits.

The Electron Spin in Nanoelectronics

While the silicon-based CMOS electronics is entering the nano-regime, it is preparing itself to accept new materials for increasing the functionality of the future IC’s. One example is the integration of magnetic multilayer nanostructures for creating a new generation of Magnetic Random Access Memories. Proven functionality in magnetic devices with nanoscale dimensions is a key asset for their use in other types of integrated devices such as lab-on-chip biosensors. This chapter will describe the technological challenges to realise the full potential of the integrated magnetic structures in which the electron spin rules the characteristics. One recognised area of future nanoelectronies is that of the use of the electron spin in semiconductor components. This field has been coined spintronics. A second part of this chapter will be devoted to the description of some of the current challenges of spintronics. Most emphasis will be placed on the issue of injecting a spin-polarized current in a semiconductor heterostructure.

EXCHANGE-BIASED MAGNETIC TUNNEL JUNCTIONS PREPARED BY IN-SITU NATURAL OXIDATION

Magnetic tunnel junctions, showing spin-dependent tunneling, are considered for future implementation in high density magnetic memories. A low device resistance is a key criterium for the implementation. In this paper, we discuss the transport properties of low-resistance tunnel barriers realized by in-situ natural oxidation of thin Al layers (< 1.3 nm). The resistance and magnetoresistance of the tunnel junctions is evaluated for different Al thickness and different oxidation times, showing tunnel magnetoresistance values of 20% for 1 kΩ.μm2. The voltage bias and temperature dependence of the transport properties is addressed, as well as the influence of thermal post-treatment.