Hans-Werner Lang

The instruction systolic array and its relation to other models of parallel computers

Abstract In this paper we investigate the relationships between three different models of parallel computers based on mesh-connected arrays: the processor array (PA), which is an MIMD-array of independent processors, the instruction broadcasting array (IBA), where the instructions are broadcast to all the processors of a column and executed according to selector information which is broadcast to all the processors of a row, and the instruction systolic array (ISA), where the instructions are pumped through the array row by row and combined with selector information which is pumped through the array column by column. For every two of these models we determine tight bounds on the worst-case delay introduced by a transformation of a program on one model into an equivalent program on the other. The results show that the ISA concept combines the advantages of standard systolic arrays with those of the MIMD concept. Since in addition the ISA architecture has smaller area requirements than a corresponding systolic array or MIMD machine it is strong practical relevance.

The instruction systolic array, a parallel architecture for VLSI

Abstract A new parallel architecture is presented that is more flexible than the systolic array: the Instruction Systolic Array (ISA). In the ISA the instructions (instead of data, as in a systolic array) are pumped through an array of processors. While systolic arrays are special purpose architectures, the ISA is more universal: It is capable of executing different programs. The Instruction Systolic Array is well suited for implementation in VLSI technology.

Instruction systolic array in image processing applications

The ISATEC parallel computer is the first implementation of an instruction systolic array for the commercial market. The goal i\of integration of 1024 processors on an add-on-board for PCs has been achieved by the development of a low- power/low-area processor architecture whose instruction set is suited particularly for image processing applications. The paper introduces the concept of the instruction systolic array, its implementation and some application examples in the field of image processing.

The Instruction Systolic Array - Implementation of a Low-Cost Parallel Architecture as Add-On Board for Personal Computers

In this paper the architecture of a 1024 processor instruction systolic array is described. Besides the presentation of the concept and the architectural details of this novel type of massively parallel system the paper focusses on the problems that had to be solved during the development phase.

Transitive closure on an instruction systolic array

The instruction systolic array (ISA) is an array processor architecture that is characterized by a systolic flow of instructions (instead of data as in standard systolic arrays). It is shown how the well-known Warshall algorithm for computing the transitive closure of a directed graph can be implemented on an n*n ISA. For problem sizes m<or=n the time complexity of this implementation is O(m).<<ETX>>

A Fast Sorting Algorithm for VLSI

An algorithm for sorting n elements in O(√n) steps is presented. Its simple structure and the fact that it needs local communication only make it suitable for an implementation by means of VLSI technology.

A bit-serial floating-point unit for a massively parallel system on a chip

This paper presents the design of a new bit-serial floating-point unit (FPU). It has been developed for the processors of the instruction systolic array (ISA) parallel computer model. In contrast to conventional bit-parallel FPUs the bit-serial approach requires a different data format. Our FPU uses an IEEE compliant internal floating-point format that allows a fast least significant bit (LSB)-first arithmetic and can be efficiently implemented in hardware. Tel.:+49-431-880-4480. Fax:+49-431-880-4054masch@informatik.uni-kiel.de Tel.:+49-461-8051235. Fax:+49-461-8051527lang@fh-flensburg.de

A Method for Realistic Comparisons of Sorting Algorithms for VLSI

A method for comparing the asymptotic performance of different sorting algorithms for VLSI is proposed. For each algorithm it takes into account the maximal problem size that is realizable on a single chip under the restrictions imposed by the available technology. This sorting chip is used to perform a sort-split operation on blocks of data in an external merge algorithm for sorting arbitrarily large sets of data. The performance of the merge algorithm is determined by the execution time and period of the sorting chip used. Thus a realistic comparison of the practical feasability of sorting algorithms for VLSI is obtained.