Hansraj Guhilot

Novel stable sram for ultra low power deep submicron cache memories

Power consumption and stability happen to be of great concern in the deep-submicron SRAM cell design. In this paper, the design and functionality of a novel ultra low power stable SRAM cell is discussed which addresses power minimization as well as stability against large variation in temperature which is ideally suited for space applications. This paper explores a novel circuit level approach to reduce power in the SRAM cell during active mode of operation as well as standby mode by incorporating NMOS-PMOS pair in each pull down path. During active mode power reduction takes place by increasing the impedance of the ground path and thus reducing the current. In the idle mode, the state of the SRAM cell is retained to a good logic-1(0) value and sub threshold leakage is reduced by utilizing stack effect. It is found that this cell operating at a supply voltage value of 0.5V, using 50nm BSIM models resulted in about 19X power savings in active mode and 21X times in stand-by state-retention mode. Better stability is also reported with large variations in temperature when compared to the standard 6-T SRAM cell and other representative low leakage power SRAM cells due to self controlling feedback. The NMOS- PMOS pair provides the compensation against the linear dependence of current on temperature. This novel cell achieves excellent active mode power minimization (which is usually not addressed in SRAM designs which achieve standby mode power minimization) along with good leakage power reduction.

Area efficient vernier Time to Digital Converter(TDC) with improved resolution using identical ring oscillators on FPGA

We present an area efficient Time to Digital Converter (TDC) based on Vernier Principle yielding a high resolution of nearly 5ps. The TDC architecture reported in this paper uses Nutt Interpolation method i.e. comprises of coarse measurement using system clock and two controllable ring oscillators for fine measurement. Ring oscillators used in this work are identical and designed using fast carry logic. The reported improved resolution is attributed to the difference in their frequencies. The novel technique of obtaining difference in their period reduces manual efforts of designer. Two main features of this work are prototyping on a low-cost general purpose FPGA and new low cost verification methodology.

Area efficient time to digital converter (TDC) architecture with double ring-oscillator technique on FPGA for fluorescence measurement application

We present an area efficient Time to Digital Converter (TDC) yielding a high resolution of nearly 10ps. The TDC architecture reported in this paper comprises of coarse measurement using system clock and two controllable oscillators for fine resolution measurement. The reported improved resolution is attributed to the difference in their frequencies. One of the main features of the implementation is its prototyping on a low-cost FPGA.

A Monolithic Implementation of Active Inductor VLQC and Jitter Free Photon Current Detection for Bio-Luminescence SPAD Sensor

An active inductor variable load quenching circuit monolithically implemented for sensing chlorophyll fluorescence and other sensor applications like bioluminescence, tomography, and DNA fingerprints is reported for the first time in this paper. An efficient biosignal acquisition with single-photon counting facility and fast quenching and reset for Single-Photon Avalanche Diode (SPAD) is implemented in 120 nm technology. This is the first ever monolithic active inductor implementation reported for quenching and reset of SPAD pixel. It is faster compared to all previously reported AQRC and variable load quenching circuit (VLQC) monolithic implementations. Along with the principle, a detailed design is presented in 120 nm technology. Analog simulations are done using LT Spice version IV and layout is primed using Microwind 3.1. The results reveals that a 50 ps light pulse with 250 ps dead time, i.e., light pulse with repetition rate of 300 ps can be quenched and detected.

Identification of hotspots on FPGA using Time to Digital Converter and distributed tiny sensors

Fully digital time-domain temperature sensors are designed and placed at five different positions within FPGA. Five tiny pulse-generators are used as five temperature sensors. Using manual floor-planning four sensors are placed at four different corners and one at centre. Single 9-bit Time to Digital Converter is utilized for digital output coding. Vernier Time to Digital Converter with 6 picoseconds resolution is presented here. The overall design utilizes 184 logical elements of FPGA i.e. less than 1.5% of the total resources. Implemented temperature sensors give nearly 0.5°C resolution and maximum of ±1.5 LSB nonlinearity is observed over the range.

Time domain ADC using pulse shrinking TDC

In this paper, a ADC using pulse shrinking TDC is proposed. The proposed ADC include a Pulse forming circuit, Pulse shrinking TDC and a compatible Counter. Initially, input voltage is converted to a proportional time pulse and then digitized using Time to Digital Converter (TDC). We present a fully-integrated Time-to-Digital Converter based on cyclic pulse-shrinking design. The whole setup is implemented and simulated in standard 0.12um ASIC platform.

Design and implementation of line multiplier

A multiplier requires an Adder circuitry to add carry of previous result to next stage to form partial products and to get final result of multiplication. This paper presents a novel way to implement Line Multiplier without using Adders. The Adder-less Multiplier is implemented on both CMOS and FPGA platforms. In ASIC paradigm CMOS 90nm technology and on FPGA platforms Spartan-3 have been used for prototyping. Detailed architecture design and implementation steps presented here to multiply two BCD numbers.

Development of FPGA Based Network on Chip for Circumventing Spam

With the growing popularity of Internet and extensive use of E-mail as a communication media, the volume of Spam mails has seen to be growing at a phenomenal rate. The growing volume of Spam mails as well as their mutating nature annoys people and affects work efficiency significantly. The unsolicited emails or Spam’s used to be deliberated of as just a nuisance, in the past few decades, however in the last few years; their annoyance has reached to epidemic proportions. Thus the Spam mails have has really become a nightmare for every email user. This chapter presents Anti-Spam solution prototyped on Xilinx Spartan 3e FPGA and designed using Handel C. We have adopted the hardware-software co-design methodology and the same is described from scratch. Two IP cores have been designed viz. Content Addressable Memory (CAM) and Bloom Filter in Handel C and the same have been deployed on the Spartan 3e FPGA along with the customizable version of Microblaze. The main contribution is reporting the technical know how related to the co-design aspects that comprehends synergic mixture of soft IP cores of the content addressable memory (CAM) and bloom filter realized both in hardware and software with the Xilinx Microblaze processor. The toolset used for the hardware-software co-design is the Xilinx Embedded Design Kit (EDK). The design flow comprises of the IP core design in Handel-C, embedded in EDK driven by the central customized core of Microblaze.

Harnessing VLSI system design with EDA tools

Introduction.- Development of FPGA Based Network on Chip for Circumventing Spam.- Analog Front End and FPGA Based Soft IP Core for ECG Logger.- FPGA Based Multifunction Interface for Embedded Applications.- FPGA Based High Resolution Time to Digital Converter.

FPGA Based High Resolution Time to Digital Converter

In an increasingly digital domain of applications, the Digital Signal Processing (DSP) has become inevitable. With the outside environment predominantly analog, its conversion into the digital domain in order to facilitate the benefits of the matured DSP technology is also mandatory. Many a times the analog to digital converter performance becomes the bottleneck in advanced instrumentation and DSP applications. This chapter presents a Vernier Time to Digital Converter (TDC) with resolution less than 30 pS, implemented on SPARTAN III FPGA. Detailed description of the TDC using schematic editor and Verilog code ring oscillator, phase detector and counter have been described in this chapter.