Harald Simmler

Multitasking on FPGA Coprocessors

Multitasking on an FPGA-based processor is one possibility to explore the efficacy of reconfigurable computing. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture allows investigating the problems of implementing realistic multitasking. This paper explores the control software required to support task switching for an application split over the host processor - coprocessor boundary as well as the requirements and features of context saving and restoring in the FPGA coprocessor context. An FPGA coprocessor designed especially to support multitasking of such applications is described.

Preemptive multitasking on FPGAs

In exploring the efficacy of reconfigurable computing, one of the dimensions is the possibility for multitasking on an FPGA-based processor. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time. The ability to do run-time configuration and readback of FPGAs in a coprocessor architecture enables exploration of the problems of implementing realistic multitasking.

Pattern recognition algorithms on FPGAs and CPUs for the ATLAS LVL2 trigger

Recent studies of the level-two (LVL2) trigger of the ATLAS detector show that the trigger algorithms for high luminosity runs can potentially be executed in general-purpose processors, using a sequential selection scheme and a LVL1 Region-of-Interest (RoI) guidance. However, the most stringent requirements in terms of computing power come from potential B-physics events investigated at low luminosity. For these events, there is no LVL1 guidance available for the track search, therefore a global pattern recognition in the whole Inner Detector volume has to be done. Executing this task in CPUs requires the computing power of 2500 state-of-the-art CPUs and makes it therefore awkward. We describe here a distributed architecture of 120 computing nodes, each consisting of a commodity computer with a PCI FPGA co-processor board inserted, capable to perform the whole track reconstruction, thus achieving a speed-up of 20. Each node processes a full event, making use of the appropriate hardware device (FPGA/CPU) for the particular tasks. Since a full track reconstruction algorithm needs inherently parallel algorithm steps, sequential steps and floating-point arithmetic, a hybrid CPU/FPGA hardware architecture might fit the problem best.

Real-time primer design for DNA chips

The design of PCR or DNA chip experiments is a time consuming process where bioinformatics is extensively used. The selection of the primers, which are immobilized on the DNA chip, requires a complex algorithm. Based on several parameters an optimized set of primers is automatically detected for a given gene sequence. This paper describes a parallel architecture which performs the optimization of the primer selection on a hardware accelerator. In contrast to the pure software approach, the parallel architecture gains a speedup of factor 500 using a PCI based hardware accelerator. This approach allows an optimization of a specified primer set in real-time.

Real‐time primer design for DNA chips

The design of PCR or DNA chip experiments is a time‐consuming process where bioinformatics is extensively used. The selection of the primers, which are immobilized on the DNA chip, requires a complex algorithm. Based on several parameters an optimized set of primers is automatically determined for a given gene sequence.

Implementation of Cryptographic Applications on the Reconfigurable FPGA Coprocessor microEnable

Nowadays, higher demand and greater awareness on security problems lend to the study of more secure, high performance, reliable and flexible systems. To meet these demands the implementation of the Blowfish algorithm in the commercial FPGA coprocessor microEnable has been chosen to present the high performance of such FPGA based reconfigurable systems. In this paper we demonstrate, how such a system can be used to enhance the speed of cryptographic computation dramatically. We show that by using this FPGA design the Blowfish computation can be increased in speed almost by a factor of 10. The achieved results lead to the general conclusion that the use of an FPGA coprocessor is ideally suited for the execution of cryptographic algorithms regarding to execution time and flexible usage.

50 kHz pattern recognition on the large FPGA processor Enable

FPGA processors are very well suited for the implementation of image processing and pattern recognition tasks. This paper describes a particularly demanding application of this type and Enable++, the FPGA processor used. The system finds particle trades in high-energy physics detector images at a rate of 100 kHz. This requires to process a data stream of up to 500 MBytes/s in real time. The algorithm and the implementation on Enable++, a general purpose FPGA processor are described. Results from a software implementation are compared with the measurements from an implementation on the CCM. This implementation is 15 times faster than the software implementation on high end computers.

ATLANTIS—a hybrid approach combining the power of FPGA and RISC processors based on CompactPCI

This poster describes the implementation of a 400-MHz frequency counter in an XC4002XL FPGA. In addition to speed, other objectives were low power and efficient resource utilization. These objectives were met using a semisynchronous design technique where pairs of flip-flops operate as synchronous state machines that are cascaded asynchronously. XC4OOOXL CLBs each contain two flip-flops that share a common clock input. This common clock permits the pair of flip-flops to operate synchronously in spite of clock routing on local interconnect. A fully asynchronous design would waste half of the flip-flops since there would be no individual clock access. The outcome of the project was a full-featured frequency counter that operates at 400 MHz, consumes only 130 mW at the maximum input frequency, and occupies 56 CLBs, less than 90% of an XC4002XL.

The ATLAS Level-2 Trigger Pilot Project

The Level-2 Trigger Pilot Project of ATLAS, one of the two general purpose LHC experiments, is part of the on-going programme to develop the ATLAS High Level Triggers (HLT). The Level-2 Trigger will receive events at up to 100 kHz, which has to be reduced to a rate suitable for full event-building of the order of 1 kHz. To reduce the data collection bandwidth and processing power required for the challenging Level-2 task it is planned to use Region of Interest guidance (from Level-1) and sequential processing. The Pilot Project included the construction and use of testbeds of up to 48 processing nodes, development of optimised components and computer simulations of a full system. It has shown how the required performance can be achieved, using largely commodity components and operating systems, and validated an architecture for the Level-2 system. This paper describes the principal achievements and conclusions of this project.

Pattern recognition and reconstruction on a FPGA coprocessor board

High energy accelerator labs use huge detector systems to track particles. The ATLAS detector at CERN, Geneva (Switzerland), will provide complex three-dimensional images. A trigger system at the detector output is used to reduce the amount of data to a manageable size. Each trigger applies certain filter algorithms to select the very rare physically interesting events. The algorithm presented, processes data from a special detector called TRT, to generate a trigger decision within /spl ap/10 ms. System supervisors then decide together with other results whether the event will be rejected or passed to the next trigger level. Due to the restricted execution time for calculating the decision, fast pattern recognition algorithms are required. These algorithms require a high I/O bandwidth and high computing power. These reasons and the high degree of parallelism make it best suited for custom computing machines.