Hardik Shah

Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs

SDRAM is a popular off-chip memory that provides large data storage, high data rates, and is in general significantly cheaper than SRAM. There is a growing interest in using SDRAMs in safety critical application domains like aerospace, automotive and industrial automation. Some of these applications have hard real-time requirements where missing a deadline can have devastating consequence. Before integrating any hardware or software in this type of system it needs to be proven that deadlines will always be met. In practice, this is done by analyzing applications timing behavior and calculating its Worst Case Execution Time (WCET). SDRAMs have variable access latencies depending on the refresh operation and the previous accesses. This paper builds on hardware techniques such as bank interleaving and applying Priority Based Budget Scheduling (PBS) to share the SDRAM among multiple masters. Its main contribution is a technique to bound the WCET of an application accessing a shared SDRAM of a multicore architecture using the worst case access pattern. We implemented and tested an overall memory system on an Altera Cyclone III FPGA and applied the proposed WCET estimation technique. The results show that our technique produces safe and low WCET bounds.

Bounding SDRAM interference: detailed analysis vs. latency-rate analysis

The transition towards multi-processor systems with shared resources is challenging for real-time systems, since resource interference between concurrent applications must be bounded using timing analysis. There are two common approaches to this problem: 1) Detailed analysis that models the particular resource and arbiter cycle-accurately to achieve tight bounds. 2) Using temporal abstractions, such as latency-rate (LR) servers, to enable unified analysis for different resources and arbiters using well-known timing analysis frameworks. However, the use of abstraction typically implies reducing the tightness of analysis that may result in over-dimensioned systems, although this pessimism has not been properly investigated. This paper compares the two approaches in terms of worst-case execution time (WCET) of applications sharing an SDRAM memory under Credit-Controlled Static-Priority (CCSP) arbitration. The three main contributions are: 1) A detailed interference analysis of the SDRAM memory and CCSP arbiter. 2) Based on the detailed analysis, two optimizations are proposed to the LR analysis that increase the tightness of its interference bounds. 3) An experimental comparison of the two approaches that quantifies their impact on the WCET of applications from the CHStone benchmark.

Priority division: A high-speed shared-memory bus arbitration with bounded latency

In state-of-the-art multi-processor systems-on-chip (MPSoC), interconnect of processing elements has a major impact on the systems overall average-case and worst-case performance. Moreover, in real-time applications predictability of inter-chip communication latency is imperative for bounding the response time of the overall system. In shared-memory MPSoCs buses are still the prevalent means of on-chip communication for small to medium size chip-multi-processors (CMPs). Still, bus arbitration schemes employed in current architectures either deliver good average-case performance (i.e. maximize bus utilization) or enable tight bounding of worst-case-execution time. This paper presents a shared bus arbitration approach allowing high bus utilization while guaranteeing a fixed bandwidth per time frame to each master. Thus it provides high-performance to both realtime and any-time applications or even a mixture of both. The paper includes performance results obtained while executing random traffic on a shared bus implemented on a FPGA. The results show that our approach provides bus utilization close to static priority based arbitration, a fairer bandwidth distribution than Round Robin and latency guarantees identical to TDMA. With this it combines the best properties of these schemes.

Timing anomalies in multi-core architectures due to the interference on the shared resources

Timing anomalies in single-core processors have been theoretically explained and well understood phenomenon. This paper presents new timing anomalies which occur in multi-core architectures due to the interference on the shared resources. We derive formulation to capture these anomalies and provide practical evidences using real applications from the M̈alardalen WCET benchmark suit executing on NIOS II multi-core architecture on an Altera FPGA.

Measurement based WCET Analysis for Multi-core Architectures

The interference on shared resources caused by concurrently executing applications unpredictably prolongs their execution. Hence, determination of the Worst Case Execution Time (Wcet) of applications executing on shared memory multi-core processors is hard to estimate. This hinders the adoption of Commercial Off The Shelf (Cots) multi-core processors in hard real-time systems. The existing techniques opt for tailored multi-core architectures to provide high computation power at predictable execution time. However, this approach yields poor resource utilization and high costs. In this paper, we present a technique to measure the Wcet of applications on multi-core architectures using existing measurement based timing analysis tools. Our technique has a minor area impact (≈ 5%). However, this impact is limited to the emulation devices only and production chips remain unchanged. Thus, our technique does not impact performance of the Cots chips by any ways. The technique is demonstrated by measuring Wcet of benchmark applications using the RapiTime timing analysis tool. The tests are conducted on a quad-core NIOS II processor on an Altera Fpga.

The Priority Division Arbiter for low WCET and high Resource Utilization in Multi-core Architectures

Shared memory arbiters play a major role in determining the Worst Case Execution Time (Wcet) of applications executing on multi-core architectures. Apart from the produced Wcet, shared memory utilization is another important parameter which characterizes the suitability of an arbiter for a particular system. This paper compares the traditional arbiters, the Static priority (aka fixed priority), the Time Division Multiple Access (Tdma) and the Round robin against the Priority division arbiter on the above mentioned merits. The paper extends the Priority division arbiter by providing a new configuration, called h1, which is highly attractive for mixed critical systems with a single Hard Real-Time (Hrt) application. The paper derives formulas to calculate the worst case latency and the worst case memory utilization. The analysis proves that the Priority division arbiter outperforms the Tdma arbiter in memory utilization and the Round robin arbiter in the produced Wcet. Moreover, the Priority division arbiter, under the h1 mode, outperforms the Static priority arbiter in terms of the produced Wcet of the single Hrt application. The supporting evidences are achieved by conducting experiments on a quad-core NIOS architecture built on Altera Fpga. The test applications are chosen from the Mälardalen Wcet benchmark suit.