Harindranath Parameswaran

Improved First-Order Parameterized Statistical Timing Analysis for Handling Slew and Capacitance Variation

With shrinking process node sizes, the inherent effect of process variations is playing an increasingly larger factor in defining the behavior of a circuit. Conventional static timing analysis (STA) using best case/worst case analysis (BC-WC) is overly pessimistic in many cases, and could also be optimistic in some cases. This has resulted in the promotion of statistical static timing analysis (SSTA) as a method for estimating yield of a circuit in terms of timing activities. SSTA provides a robust and tractable framework where the variations of the process parameter space can be captured in one analysis and the results of the analysis can be used to predict the yield of the design (with respect to timing), along with other reports of interest such as the probability of a net being critical. A popular technique for SSTA is the first-order parameterized approach where sensitivities of the timing activities to process parameter variations are propagated through the circuit, and the probability distributions of timing activities are computed at points of interest based on these sensitivities. In this paper, we describe a methodology for taking into account the effect of input slew and output load sensitivities on path arrival sensitivities. In this paper we also describe how slew sensitivities can be propagated and provide analytical expressions for the same. We also provide experimental results to show the increase in accuracy obtained as compared with Monte-Carlo analysis

Improved Timing Windows Overlap Check Using Statistical Timing Analysis

To reduce pessimism in cross talk analysis, a key technique that is employed is the use of timing windows. However, timing windows are associated with corners, hence the use of a single corner timing windows during analysis can lead to optimism. Alternately if the timings windows from best and worst corners are combined to create a wider window, it can lead to excessive pessimism. We propose an approach based on parametrized statistical timing analysis modeling to overcome the shortcomings of the existing approaches, and to account for process variations in the defnition of timing windows. We show that this approach can overcome both the issues in the current approaches.

Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping

With decreasing process nodes and increasing design density, crosstalk analysis is a must for getting design closure in the UDSM era. In addition to this, while crosstalk analysis is complex in itself, the new process nodes are showing increasing variations of process parameters for devices and interconnect. This in turn adds more complexity to crosstalk analysis. Standard techniques of factoring in the effects of process variations (corner-based analysis) is particularly ineffective for crosstalk analysis, so we need to look at techniques of statistical analysis of crosstalk in a manner similar to that used for timing. We look at a basic infrastructure for doing statistical crosstalk analysis - and look at how it can incorporate the effects of variations in cell variations and on aggressor slew. We also look at aggressor window clustering as a technique to reduce pessimism in crosstalk - and see how this technique can be modified to take in the effect of process variations. We lay the theoretical framework for these techniques in this paper, and show the results of a prototype implementation on real designs. We show that using this framework and techniques shows a close correlation with Monte-Carlo simulations.

Variation aware extracted timing model

With shrinking process node sizes, the inherent effect of process variations is playing a larger factor in defining the behavior of a circuit. conventional static timing analysis (STA) using best case/worst case analysis is overly pessimistic, and could be optimistic also in some cases. This has resulted in the promotion of statistical static timing analysis (SSTA) as a method for estimating yield of a circuit in terms of timing activities. Model extraction is a technique that accurately captures the characteristics of interface logic of a design in the form of a timing library model and provides a capacity improvement in timing verification by more than two orders of magnitude. Timing extraction plays an important role in the hierarchical analysis flows by reducing the complexity of timing verification. Current model extraction techniques are not capable generating timing models which can be used for SSTA of the complete chip. In this work, we propose a technique for generating a Statistical (or Variation Aware) Extracted Timing Model (S-ETM) to be used in conjunction with any sensitivity based SSTA engine. We also describe a method for validating S-ETM.

Crosstalk analysis using reconvergence correlation

In the UDSM era, crosstalk is an area of considerable concern for designers, as it can have a considerable impact on the yield, both in terms of functionality and operating frequency. Methods of crosstalk analysis are pessimistic in nature and the effort is ongoing to come up with techniques that make the analysis as realistic as possible. Using information from timing analysis is one such technique where we use data about overlap in switching among nets to identify those that can potentially switch together. Existing techniques tend to look at the set of a victim and associated aggressor nets in isolation, and select a subset of aggressors based on the absolute timing windows of these nets, thus ignoring the information associated with the fanin of these nets. In reality, however, some of these nets may never switch together because the reconvergence of those nets has not being factored in. Ignoring this correlation can cause false failures being flagged, leading to increased design cycles and conservatism in the design. We propose a technique where the correlation due to reconvergence can be captured in terms of relative switching windows. We apply this technique to real designs and show that this leads to more realistic analysis for crosstalk, and that we can see a reduction in the number of violations reported. We also analyze the effective of the method statistically

Computation of Waveform Sensitivity Using Geometric Transforms for SSTA

With shrinking process node sizes, the inherent effect of process variations is playing a larger factor in defining the behavior of a circuit and this has resulted in the promotion of statistical static timing analysis (SSTA) as a method for estimating the yield of a circuit in terms of timing activities. The accuracy of SSTA depends on the accuracy of timing sensitivities as computed using a statistical delay calculation (S-DC) engine. The accuracy of the S-DC engine in turn depends on the accuracy and availability of the required information in the timing library. For statistical analysis, these libraries need to contain information on the effect that process variations have on the library timing data. New generation delay calculators also require change in waveform shape (waveform sensitivity) with process variation to be modeled in timing library for better accuracy. Waveform sensitivities are required for accurate computation of gate delay sensitivities for gates driving large interconnect loads or a large number of fanouts. However, modeling waveform sensitivities in the timing library increases the library size significantly (~40% per process parameter). Also in different scenarios the characterization of waveform sensitivities may not be possible. In this paper, we propose a technique for computing waveform sensitivities during analysis when such information is not part of the standard cell library. We use geometric transforms and the nominal waveform information, along with available sensitivities of the timing activities in non-linear delay models to derive waveform sensitivities. We show that using our approach the size of a statistical library with 700 cells is reduced by ~65% as compared to a statistical library with characterized waveform sensitivities. We also show that the computed waveform sensitivities provide an accuracy improvement of 15-20% in the computation of standard deviation.

Efficient reduction techniques for statistical model generation of standard cells

Statistical analysis has become an important technique to accurately factor in the effect of process variations in circuit behavior. Statistical analysis techniques depend on the generation of compact, fast, accurate and robust models that capture some specific aspect of the circuit behavior. The process of characterizing the circuit behavior to generate variation-aware models for standard cells has a large runtime penalty (l00x of nominal model generation). This runtime explosion is primarily due to the additional numbers of simulations required to capture the effects of within-die (WID) variations. We look at the techniques used for capturing WID effects in model generation and present some techniques to reduce the runtime of statistical delay and leakage characterization significantly. We show that our technique can speed up timing model generation by l0x and leakage model generation by approximately 2x.