Harold Dekkers

Metal gate work function tuning by Al incorporation in TiN

Titanium nitride (TiN) films have been used as gate electrode on metal-oxide-semiconductor (MOS) devices. TiN effective work function (EWF) values have been often reported as suitable for pMOS. For nMOS devices, a gate electrode with sufficient low EWF value with a similar robustness as TiN is a challenge. Thus, in this work, aluminum (Al) is incorporated into the TiN layer to reduce the EWF values, which allows the use of this electrode in nMOS devices. Titanium aluminum (TiAl), Al, and aluminum nitride (AlN) layers were introduced between the high-k (HfO2) dielectric and TiN electrode as Al diffusion sources. Pt/TiN (with Al diffusion) and Pt/TiN/TiAl/TiN structures were obtained and TiN EWF values were reduced of 0.37u2009eV and 1.09u2009eV, respectively. The study of TiN/AlN/HfO2/SiO2/Si/Al structures demonstrated that AlN layer can be used as an alternative film for TiN EWF tuning. A decrease of 0.26u2009eV and 0.45u2009eV on TiN EWF values were extracted from AlN/TiN stack and AlN/TiN laminate stack, respectively. AlN/TiN laminate structures have been shown to be more effective to reduce the TiN work function than just increasing the AlN thickness.

High-efficiency low-cost integral screen-printing multicrystalline silicon solar cells

This paper describes how the efficiency and throughput of industrial screen-printed multi-Si solar cells can be increased far beyond the state-of-the-art production cells. Implementation of novel processes of isotropic texturing, shallow emitter or single diffusion selective emitter, combined with screen-printed metallization fired through a PECVD SiNx ARC layer, have been described. Novel dedicated fabrication equipment for emitter diffusion and a PECVD SiNx deposition system are developed and implemented thereby removing the processing bottlenecks linked to the diffusion and bulk passivation processes. Several types of back-contacted solar cells with improved visual appeal required for building integrated photovoltaic (BIPV) application have been developed.

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

This paper discusses the approach for patterning 15nm Half Pitch (HP) structures using EUV lithography combined with Self-Aligned Double Patterning (SADP). A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of LWR, LER and CDU, targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER and CDU at 15nm HP are demonstrated.

Spacer defined double patterning for (sub-)20nm half pitch single damascene structures

The spacer defined double patterning (SDDP) approach for 20nm half pitch (HP) single damascene Cu interconnect structures using immersion lithography is being reviewed. Final results on wafer will be shown, focusing on critical double patterning topics such as CD & overlay budget and line edge roughness (LER); and their impact on the electrical functioning of the back-end-of-line test structures. The feasibility of extending the SDDP technique down to 15nm HP structures is also discussed. The 30nm line/space structures patterned in resist, required as a starting point for this exercise, will be patterned using EUV lithography.

Wafer-shape based in-plane distortion predictions using superfast 4G metrology

With the latest immersion scanners performing at the sub-2 nm overlay level, the non-lithography contributors to the OnProduct-Overlay budget become more and more dominant. Examples of these contributors are etching, thin film deposition, Chemical-Mechanical Planarization and thermal anneal. These processes can introduce stress or stress changes in the thin films on top of the silicon wafers, resulting in significant wafer grid distortions. High-order wafer alignment (HOWA) is the current ASML solution for correcting wafers with a high order grid distortion introduced by non-lithographic processes, especially when these distortions vary from wafer-to-wafer. These models are currently successfully applied in high volume production at several semiconductor device manufacturers. An important precondition is that the wafer distortions remain global as the polynomial-based HOWA models become less effective for very local distortions. Wafer-shape based feed forward overlay corrections can be a possible solution to overcome this challenge. Thin film stress typically has an impact on the unclamped, free-form shape of the wafers. When an accurate relationship between the wafer shape and in-plane distortion (IPD) after clamping is established then feedforward overlay control can be enabled. In this work we assess the capability of wafer-shape based IPD predictions via a controlled experiment. The processinduced IPDs are accurately measured on the ASML TWINSCANTM system using its SMASH alignment system and the wafer shapes are measured on the Superfast 4G inspection system. In order to relate the wafer shape to the IPD we have developed a prediction model beyond the standard Stoney approximation. The match between the predicted and measured IPD is excellent (~1-nm), indicating the feasibility of using wafer shape for feed-forward overlay control.

Bulk Passivation of Defects in Multi-Crystalline Silicon Solar Cells by a-SiNx:H Layers

In this work the impact of hydrogenation from hydrogen-rich amorphous silicon nitride (a-SiNx:H) on dislocations and grain boundaries in multi-crystalline silicon (mc-Si) solar cells is presented. Layers are deposited by means of plasma enhanced chemical vapor deposition (PECVD). Electrical bulk passivation is provided during thermal annealing, in which hydrogen diffuses from a-SiNx:H. The passivation effect is discussed in terms of recombination centers and non-recombinative charge traps reduction as well as in terms of local short circuit current improvement in specially manufactured solar cells.

RMG Patterning by Digital Wet Etching of Polycrystalline Metal Films

A self-limiting wet etching of metal thin films has been developed for the replacement metal gate patterning in advanced logic devices, which will have aggressively scaled gate length and fin pitches. A uniform and highly selective wet etching of polycrystalline TiN films is demonstrated by a diffusion-limiting oxide growth on the metal surfaces as well as a subsequent highly selective oxide removal.