Harold W. Carter

Fast multivariate signature generation in hardware: The case of rainbow

This paper deals with the design of an area-time efficient hardware architecture for the multivariate signature scheme, Rainbow. As a part of this architecture, a high-performance hardware optimized variant of the well-known Gaussian elimination over GF(2l) and its efficient implementation is presented. Besides solving LSEs, the architecture is also re-used for the linear transformation operations of the scheme, thereby saving on area. The resulting signature generation core of Rainbow requires 63,593 gate equivalents and signs a message in just 804 clock cycles. A comparison of our architecture with implementations of the RSA, the ECDSA and the en-TTS scheme shows that Rainbow in hardware provides significant performance improvements.

Synchronous global clock distribution on multichip modules using optical waveguides

A novel optical waveguide H-tree design for synchronous global clock distribution on multichip modules, which has nearly zero clock skew, is developed for a distributed computer system environment. The optical waveguide H-tree design utilizes channel waveguides, curved sections, and directional couplers formed using silica glass and silicon oxynitride channel waveguide technologies. Design calculations are presented comparing these technologies that suggest a hybrid combination having the advantages of each. System performance analysis is carried out for both waveguide technologies and the hybrid combination. These calculations demonstrate the feasibility of this approach and show that the achievable clock speed is limited by the laser diode source and photodiode receiver at each chip module, and not by the optical waveguide distribution network.

SEAMS: simulation environment for VHDL-AMS

VHDL-AMS is an analog and mixed-signal extension to the Very High Speed Integrated Circuit Hardware Description Language (VHDL). With the standardization of VHDL-AMS, capable and efficient simulators are in demand for exercising complex analog and mixed-signal models. The simulation of the language requires the ability to handle several levels of design hierarchy, the combination of multiple domains of modeling and the synchronization of continuous and discrete-event simulation. The expressive power of VHDL-AMS is also conducive for creating large simulation models. Large models have high resource demands especially on memory and execution time making parallel simulation no longer an option but a requirement. This paper introduces the issues involved in the design of a VHDL-AMS simulator and illustrates the simulation approach provided by SEAMS a parallel VHDL-AMS simulator. A performance study is presented to analyze the effectiveness of mixed-signal simulation using SEAMS.

A formal specification and verification framework for Time Warp-based parallel simulation

The paper describes a formal framework developed using the Prototype Verification System (PVS) to model and verify distributed simulation kernels based on the Time Warp paradigm. The intent is to provide a common formal base from which domain specific simulators can be modeled, verified, and developed. PVS constructs are developed to represent basic Time Warp constructs. Correctness conditions for Time Warp simulation are identified, describing causal ordering of event processing and correct rollback processing. The PVS theorem prover and type-check condition system are then used to verify all correctness conditions. In addition, the paper discusses the frameworks reusability and extensibility properties in support of specification and verification of Time Warp extensions and optimizations.

Modeling and simulating semiconductor devices using VHDL-AMS

The VHDL-AMS language supports the description of analog electronic circuits using Ordinary Differential Algebraic Equations (ODAEs), in addition to its support for describing discrete-event systems. For VHDL-AMS to be useful to the analog design community, efficient semiconductor device model must be available. This paper attempts to exploit the rich expressiveness of VHDL-AMS to describe semiconductor device models. The device models for diodes and transistors have been developed in VHDL-AMS and were validated using SEAMS, a mixed-signal simulator under development at the Distributed Processing Laboratory, University of Cincinnati.

Optimizing costs of web-based modeling and simulation

Web-based simulations are performed by utilizing the resources of the Word Wide Web (WWW) such as proprietary components/models developed by third party modelers/manufacturers and web-based computational infrastructures (or compute servers). Access to such web-based resources, third party resources in particular, is usually circumscribed by a variety of pricing schemes. Therefore, optimal use of resources plays a critical role in minimizing the overall costs of web-based modeling and simulation which is directly dependent on the size of the model i.e., the total number of components constituting the model. Consequently, component aggregation and de-aggregation techniques that can be used to statically (before simulation) as well as dynamically (during simulation) vary the number of components constituting a model, have been developed. The techniques enable a range of tradeoffs between several modeling and simulation related parameters – thereby optimizing the resource consumption and overall costs. This paper presents a detailed discussion of the component aggregation and de-aggregation techniques along with the issues involved in implementing them in a Web-based Environment for Systems Engineering (WESE). Our studies indicate that these techniques provide an effective means to optimize the overall costs of web-based modeling and simulation.

Performance comparison of global clock distribution networks on multichip modules based on electrical and optical interconnect technologies

A high-speed low-skew system clock distribution network on a multichip module (MCM) is considered in systems perspective using system bandwidth, allowable system switching energy, number of clock signal fanout nodes supported, and the flexibility of the network structure to accommodate placement and routing requirements of various integrated circuits on MCM. Electrical H-tree networks modeled as lossless transmission lines are designed and evaluated along with guided wave optical H-tree networks. System performance analysis of optical and electrical H-tree networks on MCM suggests that optical H-tree clock distribution network has a superior capability compared to the electrical one by providing larger bandwidth, larger fanout, smaller system switching energy, and a flexible network configuration.

Parallel synchronization of continuous time discrete event simulators

Mixed-Mode simulation has been generating considerable interest in the simulation community and has continued to grow as an active research area. Traditional mixed-mode simulation involves the merging of digital and analog simulators in various ways. However, efficient methods for the synchronization between the two time domains remains elusive. This is due to the fact that the analog simulator uses dynamic time step control whereas the digital simulator uses the event driven paradigm. This paper proposes two new synchronization methods and presents their capabilities using a component-based continuous time simulator integrated with an optimistic parallel discrete event simulator. The results of the performance evaluation leads us to believe that while both synchronization methods are functionally viable, one has superior performance.

Fast Multivariate Signature Generation in Hardware: The Case of Rainbow

This paper presents a time-area efficient hardware architecture for the multivariate signature scheme Rainbow. As a part of this architecture, a high-performance hardware optimized variant of the well-known Gaussian elimination over GF(2l) and its efficient implementation are presented. The resulting signature generation core of Rainbow requires 63,593 gate equivalents and signs a message in just 804 clock cycles at 67 MHz using AMI 0.35 mum CMOS technology. Thus, Rainbow provides significant performance improvements compared to RSA and ECDSA.

Realization of an analog biquadratic filter using log-domain techniques

We propose the design of a biquadratic filter using log domain filtering techniques. The filter is designed using a purely current-mode approach. This biquadratic filter realizes low pass, high pass, band pass, band elimination and all pass filter functions. The designed filter is electronically tunable over several decades of frequency by changing the magnitude of current source. The complexity is low as current mirrors are used as opposed to operational amplifiers, gyrators or OTAs.