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Harpreet Sachar

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Publication

Featured researches published by Harpreet Sachar.

Archive | 2005

SONOS memory cell having high-K dielectric

Takashi Whitney Orimoto; Joong Jeon; Hidehiko Shiraiwa; Simon S. Chan; Harpreet Sachar

Archive | 2002

Shallow trench isolation approach for improved STI corner rounding

Unsoon Kim; Yu Sun; Hiroyuki Kinoshita; Kuo-Tung Chang; Harpreet Sachar; Mark S. Chang

Archive | 2004

One stack with steam oxide for charge retention

Hidehiko Shiraiwa; Harpreet Sachar; Mark Randolph; Wei Zheng

Archive | 2005

System and method for improving reliability in a semiconductor device

Yider Wu; Unsoon Kim; Kuo-Tung Chang; Harpreet Sachar

Archive | 2010

USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FLASH MEMORY CELL TO IMPROVE TPD CHARACTERISTICS

Ning Cheng; Calvin Gabriel; Angela Hui; Lei Xue; Harpreet Sachar; Phillip Lawrence Jones; Hiro Kinoshita; Kuo-Tung Chang; Huaqiang Wu

Archive | 2006

Non-critical complementary masking method for poly-1 definition in flash memory device fabrication

Unsoon Kim; Hiroyuki Kinoshita; Yu Sun; Krishnashree Achuthan; Christopher H. Raeder; Christopher M. Foster; Harpreet Sachar; Kashmir Sahota

Archive | 2006

Memory system with protection layer to cover the memory gate stack and methods for forming same

Hidehiko Shiraiwa; YouSeok Suh; Harpreet Sachar; Satoshi Torii

Archive | 2005

Non-volatile memory device with improved erase speed

Joong Jeon; Takashi Whitney Orimoto; Robert B. Ogle; Harpreet Sachar; Wei Zheng

Archive | 2007

Nand memory with silicon-rich charge storage layers and manufacturing method thereof using self-aligned shallow-trench isolation

Amol Joshi; Harpreet Sachar; YouSeok Suh; Shenqing Fang; Chih-Yuh Yang; Lovejeet Singh; Hidehiko Shiraiwa; Kuo-Tung Chang; Scott Bell; Allison Holbrook; Satoshi Torii; David Matsumoto

Archive | 2006

Oxygen elimination for device processing

Boon-Yong Ang; Hidehiko Shiraiwa; Simon S. Chan; Harpreet Sachar; Mark Randolph

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