Harry C. Gundrum

A microprocessor-based dynamic inductance/capacitance meter

A microprocessor-based dynamic inductance/capacitance meter has been developed. Two different approaches are examined utilizing the frequency response of the circuit where the unknown reactive element is included. One procedure uses an LC oscillator which generates a frequency that is proportional to the reactive elements, while the other employs the resonance response of an RLC circuit from which the unknown element can be determined by the phase relationship. An 8088 processor detects the frequency counts in the first procedure, monitors the phase relationship in the second, and performs the required calculations for both. The microprocessor periodically samples the output of the LC oscillator at its input port to dynamically monitor the changes in the reactive circuit elements. Within 5% error over the frequency range of 100 Hz to 256 kHz, a wide range of inductance and capacitance values for both approaches were determined.<<ETX>>

Blocking artifacts reduction for image compression algorithms

In this paper, a new algorithm is proposed to improve the performance of the existing JPEG image compression algorithm. The algorithm proposes a recursive pruned discrete cosine transform (DCT) to reduce the bit rate and two different methods to reduce the image artifacts arising at these lower bit rates. The recursive algorithm computes the pruned DCT using a structure that allows the generation of higher order pruned DCT from two identical, lower order pruned DCTs. A variance dependent pruning method determines the pruning based on the statistical properties of the image block. A linear filtering method performs low pass filtering on the block boundaries for smoothing the discontinuities.

ASIC memory design of 2-D median filters

An 8-bit VHDL based 2-D median filter is designed using Mentor Graphic tools. The algorithm is based on sorting pixel samples and extracting their median values. The code was synthesized and optimized for an IC layout using CMOS 2 micron technology. The principal organization of the memory elements to store data that perform two dimensional transpose application is presented. A Matlab program for this algorithm was written, tested, and verified on 400/spl times/400 pixel images.

Maximizing the stability region for a second order PLL system

In this work, a general second order scheme using a geometric approach for determining the stability bounds of a system described in the state variables is developed. This scheme is applied to Phase-locked Loop systems, PLLs, to optimize the eigenvalues by shifting the pole locations of the low pass filter of the PLLs for maximum range of stability. The system has been utilized in frequency synthesis applications and the maximum range of stability is demonstrated at various step frequencies. The maximum range of the stability is determined. The simulations of a general second order PLL system is demonstrated and the results of the phase plane plots show a general agreement with the analysis.

Linville power plane stability and bandwidth improvements in a minimum-drift video amplifier

The stability of a previously designed, minimum-drift video amplifier is studied over a wide bandwidth. An original upper frequency of 2 MHz has been extended to 20 MHz using high-frequency compensation techniques. The Y-parameters were measured at 3.0 MHz and used in the Linville power plane to determine the input and output power curves. Two techniques for enhancing the system response have been investigated. In the mismatch method, a stem stability factor was chosen to keep the system stability over a wide band of frequencies. The neutralization method in which the intrinsic feedback parameter Y/sub 12/ is neutralized is discussed. While both methods show acceptable stability improvements, the mismatch method is used because it does not require an additional transformer to the system. The video amplifier LM733 driven by the N-channel BFR84 MOSFET has been used for demonstration.<<ETX>>

VHDL implementation of a 2-D uniform coefficient FIR filter

This work presents a new VHDL design methodology and performance of a 2-D uniform finite impulse response (UCFIR) digital filter. The approach is analogous to that of the 2-D discrete cosine transform (DCT) in image processing applications. A set of 64 two-dimensional cosine basis functions are created by multiplying a horizontally oriented set of one-dimensional 8-point basis functions by a vertically oriented set of the same functions. The design was simulated, synthesized and optimized using Mentor Graphics software tools. The simulation results of the design were verified using MatLab imaging tools.

Simulating discrete system pole location data with 3D effects using circular functions and determinants

The identities of two circular functions are used, through a geometric construction onto a unit circle representing the z-domain of discrete systems, to generate a set of planar triangles from which both edge length and area can be used to build and model a 3D data structure of the system.

VLSI design for a forward path neuron circuitry of a back propagation neural network

This paper describes the hardware design and implementations of the forward path for the back propagation algorithm of an analog neural network. The design considers the voltage range for fractional and floating point processing in multimedia applications. The PSpice simulation using MOSIS device parameters are presented.

A CMOS VLSI implementation of an N/spl times/N multiplexing circuitry for ATM applications

A non internal blocking ATM packet switching network using CMOS technology has been developed for an N/spl times/N switch. A multiplexing circuitry with 32 inputs was designed and implemented using simple logic gates. The development has utilized an interconnection network of 1/spl times/32 parallel expander circuits. The control unit consisting of serial shift registers and latches to keep the destination path open for the length of the packet, were designed using MAGIC software and simulated by IRSIM. As low as 5 ns delay was estimated by the 1/spl times/32 expander circuit, while the clock generated by the combinational circuit for latching showed a delay of 190 ns. The system has been fabricated using MOSIS services, and as minimum of 5 ns delay was measured between the input and output nodes of the switching circuit.

Fast pruned dental caries classifiers

In this paper, we propose two new algorithms that use the pruned fast Fourier transform to generate the input to a backpropagation neural network of a dental caries classifier. The proposed systems eliminate the generation of digital sampling detector lookup table and the extraction of spectral feature vectors using the digital sampling detector. The proposed algorithms greatly reduced the number of complex multiplications and improved the speed-up factors.