Harry Siebert

Debug support, calibration and emulation for multiple processor and powertrain control SoCs [automotive applications]

The introduction of complex SoCs with multiple processor cores presents new development challenges, such that development support is now a decisive factor when choosing a system-on-chip (SoC). The presented development support strategy addresses the challenges using both architecture and technology approaches. The multi-core debug support (MCDS) architecture provides flexible triggering using cross triggers and a multiple core break and suspend switch. Temporal trace ordering is guaranteed down to cycle level by on-chip time stamping. The package sized-ICE (PSI) approach is a novel method of including trace buffers, overlay memories, processing resources and communication interfaces without changing device behavior. PSI requires no external emulation box, as the debug host interfaces directly with the SoC using a standard interface.

Boosting Debugging Support for Complex Systems on Chip

Advanced on-chip debug support can help overcome the challenges of developing real-time embedded systems driven by complex SoCs, making development support a decisive selection factor. One novel approach supports the on-time development of high-quality complex systems without greatly increasing the required design and production resources