Hartmut Wittke

Live Sequence Charts

The language of Message Sequence Charts (MSC) is a well-established visual formalism which is typically used to capture scenarios in the early stages of system development. But when it comes to rigorous requirements capturing, in particular in the context of formal verification, serious deficiencies emerge: MSCs do not provide means to distinguish mandatory and possible behavior, for example to demand that a communication is required to finally occur.

The Statemate Verification Environment

The STATEMATE Verification Environment supports requirement analysis and specification development of embedded controllers as part of the STATE-MATE product offering of I-Logix, Inc. This paper discusses key enhancements of the prototype tool reported in [2,5] in order to enable full scale industrial usage of the tool-set. It thus reports on a successfully completed technology transfer from a prototype tool-set to a commercial offering. The discussed enhancements are substantiated with performance results all taken from real industrial applications of leading companies in automotive and avionics.

Formal Verification of an Avionics Application using Abstraction and Symbolic Model Checking

This paper demonstrates the use of model-checking based verification technology to establish safety critical properties for an industrial avionics application. The verification technology is tightly integrated with the Statemate ® system of i-Logix Inc., USA. Key features of this technology are its scalalability to complete system verification, the powerful debugging capabilities, graphical entry for safety critical properties, and the capability to re-use verification results for design components. The paper describes the application, the Statemate verification environment, and its use to establish safety critical properties of a British Aerospace application. The technical focus is on the use of abstraction techniques, allowing to focus verification on aspects of the design relevant to the property under investigation.

Formal Verification of LSCs in the Development Process

This paper presents how a model-based development process can be enhanced by the combination of using Live Sequence Charts (LSC) as the formal language to describe interactions together with automatic formal verification techniques that decide whether communication sequences are exhibitable or adhered to by the system. We exemplify our approach on the V-model, a widely used development process, considering a (Statemate) statecharts design of the reference case study “Funkfahrbetrieb” (FFB) and discuss potential assets and drawbacks. We sketch a set of best practices on the use of LSC features and emphasise the possibilities for re-use of LSCs in the different activities of the development process. To give evidence for feasibility of automatic formal verification of LSCs, as well as its limitations, we present our approaches to the verification of possible and mandatory LSC requirements on Statemate models. We report experimental results we have obtained from formal verification of the FFB and briefly discuss the treatment of Statemate’s different notions of time.

Formale Analyse und Verifikation von Statemate-Entwürfen (Formal Analysis and Verification of Statemate Designs)

Dieser Artikel gibt einen Überblick über die Statemate-Verifikationsumgebung und ihre Anwendung zur Verifikation von eingebetteten Steuerungssystemen. Ein Schwerpunkt liegt auf der Präsentation von neu eingeführten Analysetechniken sowie der Integration von Live Sequence Charts, einer Erweiterung von Message Sequence Charts.