Harumi Ikeda

0.9µm pitch pixel CMOS image sensor design methodology

We demonstrate the first ever 0.9µm pitch pixel CMOS image sensor(CIS), and reveal the problems that are likely to be encountered in future device structures. We have developed a set of guidelines for the design of high quantum efficiency(QE) CISs, and verified their validity by comparing the image quality of 0.9, 1.12, 1.4 and 1.75µm CISs. Furthermore, we propose a simple methodology to optimize more complicated submicron pitch CIS structures.

IR sensitivity enhancement of CMOS Image Sensor with diffractive light trapping pixels

We report on the IR sensitivity enhancement of back-illuminated CMOS Image Sensor (BI-CIS) with 2-dimensional diffractive inverted pyramid array structure (IPA) on crystalline silicon (c-Si) and deep trench isolation (DTI). FDTD simulations of semi-infinite thick c-Si having 2D IPAs on its surface whose pitches over 400 nm shows more than 30% improvement of light absorption at λ = 850 nm and the maximum enhancement of 43% with the 540 nm pitch at the wavelength is confirmed. A prototype BI-CIS sample with pixel size of 1.2 μm square containing 400 nm pitch IPAs shows 80% sensitivity enhancement at λ = 850 nm compared to the reference sample with flat surface. This is due to diffraction with the IPA and total reflection at the pixel boundary. The NIR images taken by the demo camera equip with a C-mount lens show 75% sensitivity enhancement in the λ = 700–1200 nm wavelength range with negligible spatial resolution degradation. Light trapping CIS pixel technology promises to improve NIR sensitivity and appears to be applicable to many different image sensor applications including security camera, personal authentication, and range finding Time-of-Flight camera with IR illuminations.