Hassan Aboushady

A 1.3V 26mW 3.2GS/s undersampled LC bandpass ΣΔ ADC for a SDR ISM-band receiver in 130nm CMOS

This paper presents the implementation of an undersampled LC bandpass ΣΔ ADC with a raised-cosine feedback DAC. It directly converts after the LNA a signal centered in the ISM band at 2.442GHz with a sampling frequency of 3.256GHz. This circuit has been fabricated in a 130nm CMOS process, it occupies an area of 0.27mm2 and is operating at a supply voltage of 1.3V. The Signal-to-Noise and Distortion Ratios measured are 34dB, 37dB and 42dB for respective bandwidths of 25MHz, 10MHz and 1MHz. The power consumption of the ΣΔ ADC is 26mW and its figure of merit is 2.3pJ/bit.

Systematic approach for scaling coefficients of discrete-time and continuous-time sigma-delta modulators

In this paper we present a systematic method to scale the integrators output swings of /spl Sigma//spl Delta/ modulator. It is shown that this scaling method preserves both the noise transfer function and the signal transfer function of the modulator. Examples are given to illustrate the effectiveness of the proposed method to alleviate circuit non-idealities.

A 4 th order subsampled RF ∑Δ ADC centered at 2.4GHz with a sine-shaped feedback DAC

A 4th order subsampled RF LC ∑Δ ADC suitable for Software Defined Radio applications is presented. The ADC is clocked at 3.2GHz and centered at 2.4GHz. The simplicity of the ADC architecture combined with the subsampling technique result in a significant performance enhancement and power consumption reduction. A sine-shaped feedback DAC is used, not only for its reduced sensitivity to clock jitter but also for its more convenient frequency response to subsampled ∑Δ ADCs. An efficient algorithm for the tuning and calibration of the LC-based loop filter is presented. The ADC is implemented in a standard 130nm CMOS technology. It achieves a 51dB SFDR and a 40dB SNDR in a 25MHz BW and consumes only 19mW from a 1.2V supply.

Automatic model refinement of GmC integrators for high-level simulation of continuous-time Sigma-Delta modulators

A ΣΔ GmC integrator refinement flow is presented. The classically simplified GmC integrator small-signal model was upgraded to be extremely accurate by considering the complete transistor small-signal model. A circuit-level knowledge-based tool was used to execute the designer defined sizing procedure and to extract small signal parameters. By associating the symbolic transfer function to small-signal parameters, the flow, entirely implemented with C++, is able to compute poles and zeros to permit precise behavioral simulations. A 2nd order ΣΔ modulator was chosen to visualize performance degradations while the specifications were not achievable.

Sinusoidal RF DACs for undersampled LC bandpass ∑Δ modulabrs

In this paper, we present a systematic technique to design bandpass LC Sigma Delta modulators with sinusoidal feedback DACs. The output resistance of the DAC degrades the quality factor of the LC resonator and the DAC output capacitance modifies its resonance frequency. It is shown that the DAC output resistance should be taken into account while designing the Q enhancement circuit of the integrated LC resonator. The resonance frequency is adjusted by modifiying the parallel capacitor of the LC resonator. Using the proposed method, different sinusoidal 3.256 GHz DACs are designed in a CMOS 0.13 mum process. Simulation results are presented to compare their performances in the context of an undersampled LC SigmaDelta modulator.

A Constant Temperature Thermoresistive Sigma-Delta Anemometer

In this paper we propose a feedback measurement system, with thermoresistive sensor, based on sigma-delta modulation. The system uses a one-bit sigma-delta modulator for which a considerable part of the conversion functions is performed by a thermoresistive sensor. The sensor is modelled using the power balance principle and the constant temperature measurement method is employed. This transducer architecture is able to realize digital measurement of physical quantities that interacts with the sensor: temperature, thermal radiation and fluid velocity. This paper presents simulations and validates the structure of the sigma-delta converter as an anemometer. The advantage to directly convert physical quantities to digital, with the sensor as part of the A to D converter, makes possible the implementation of this measurement system in an integrated circuit. Another advantage of the IC implementation of this structure is the possibility to reduce noise interference due to discrete component connections in a printed circuit board.

CMOS sigma-delta thermal modulator

This work presents the design of a 1st-order sigma-delta thermal modulator using a thermoresistive sensor in its feedback loop, as the summing and integrating elements. The proposed system architecture allows the measurement of physical quantities that interact with the sensor, as temperature, thermal radiation and fluid velocity. Procedures for obtaining the design specifications needed for its modeling in VHDL-AMS are presented. A layout for the sigma-delta thermal modulator was developed for the integrated circuit technology CMOS 0.35 µm. Simulation results from this layout for temperature measurement are presented, showing that a resolution of 8.7 bits was attained, for a input signal frequency range of 12.5 kHz and a sampling frequency of 25.6 MHz.

Filtering adjacent channel blockers using signal-transfer-function of continuous-time /spl Sigma//spl Delta/ modulators

In this paper, we show that the signal transfer function of continuous-time /spl Sigma//spl Delta/ modulators can be used to remove the baseband analog filters in radio receivers. General expressions for the signal transfer function of continuous-time /spl Sigma//spl Delta/ modulators are derived. Comparisons between the frequency response of feedforward and feedback architectures of discrete-time and continuous-time /spl Sigma//spl Delta/ modulators are established. Filtering of GSM adjacent channel blockers using a 5/sup th/ order continuous-time /spl Sigma//spl Delta/ is given as an example.

An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm

An FPGA implementation of an all-digital fully compliant IEEE 802.11b and 802.15.4 configurable baseband receiver is presented. This architecture can be integrated in systems implementing the Software Defined Radio (SDR) paradigm, relaxing the need for high power consumption general purpose processors. The receiver uses a single architecture that can be configured for receiving either standard at run time, exploiting similarities between both protocols, and may serve as a coprocessor for offloading the task of processing baseband RF signals. The system can be used as a platform for future low power devices to integrate into the SDR paradigm. Results showed that the architecture exceeds the specifications required by both standards, and has great performance in low SNR scenarios, making it an attractive alternative in wireless sensor networks with extremely low signal power levels.

The design of RF bandpass ΣΔ modulator with bulk acoustic wave resonators

This paper proposes a method to introduce BAW resonators in the loop of a Continuous-Time Sigma-Delta modulator. The method is based on the equivalence between the Noise-Transfer-Function of a conventional bandpass Discrete-Time Sigma-Delta and the Noise-Transfer-Function of a Continuous-Time BAW-based Sigma-Delta modulator with FIRDACs. The method is general and can be applied to BAW resonators with and without cancellation of the anti-resonance frequency. The Noise-Transfer-Function and the Signal-Transfer-Function of the BAW-based Sigma-Delta modulator are analyzed and compared with their Discrete-Time counterpart.