Hassan Diab

Defuzzification techniques for fuzzy controllers

Based on the features and disadvantages of the commonly used defuzzification techniques and on the elements involved in the structure of a fuzzy controller, a new and advantageous defuzzification technique is introduced and justified. This is done by integrating the defuzzification problem into the global structure of fuzzy controllers. Another related defuzzification strategy, which has been introduced elsewhere by the principle author of this study, is also given and commented upon. Further, case studies are considered and comparative conclusions are drawn.

A computer-aided teaching package for microprocessor systems education

A computer-aided teaching (CAT) package for use in a microprocessor systems course is described. It uses the Z80 CPU as the basis for describing how an eight-bit CPU functions internally and as the master of a microcomputer system. The package, which consists of an assembler and a graphics simulator, aids as a powerful teaching tool that enables the student to learn about the internal architecture of a microprocessor as applied to the Z80 CPU and its instruction set with a step-by-step graphics animation of the instruction execution and timing. The package allows the user to execute a program step by step and to test the operation of the internal registers, buses, and memory contents at every clock edge. It also simulates read/write cycles from/to memory and input-output devices. Finally, it allows the user to write and debug problems at the assembly language or machine code level. The package is menu driven, interactive, flexible, and user-friendly. >

Performance analysis of extended vector-scalar operations using reconfigurable computing

This paper maps a new application, namely vector-scalar operations, onto the M1 MorphoSys (from UCI) reconfigurable computing system. A performance analysis study of the M1 RC is also presented to evaluate the efficiency of the algorithm execution on the M1 system. For instance, two algorithms on an 8/spl times/8 RC array M1 were run, and numerical examples were simulated to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operation.

Reconfigurable computing for RC6 cryptography

This paper presents an emerging reconfigurable hardware that potentially delivers flexible high performance for cryptographic algorithms. MorphoSys, a dynamic reconfigurable architecture that sustains implementations that can yield into equally or even better performance results than custom-hardware and yet preserves all the flexibility of general-purpose processors. With todays great demand for secure communications systems, networks and the Internet, there is a growing demand for real-time implementation of cryptographic algorithms. As a case study, this paper presents the mapping and performance analysis for one of the five AES finalists cryptographic algorithms, namely RC6. Being an important and secure cryptographic algorithm, RC6 is considered well chosen to be mapped in order to test and evaluate the suitability of dynamic reconfigurable computer (RC) systems such as MorphoSys.

Serpent Cryptography on Static and Dynamic Reconfigurable Hardware

This paper presents parallel reconfigurable hardware implementations of the Serpent (AES Finalist) cryptographic algorithm. Currently, Serpent is well known to be a simple but very strong encryption algorithm. The use of such an algorithm within critical applications, such as banking and military, requires efficient and highly reliable hardware implementation. We will stress the affordability of such requirements by analyzing and evaluating parallel Serpent implementations using static and dynamic reconfigurable systems. The used systems are the MorphoSys dynamically reconfigurable computer and The RC-1000 statically reconfigurable system from Celoxica Ltd with its 2 million gates Xilinx Virtex-E FPGA. In this paper, different designs for the Serpent corresponding to different Degrees of parallelism are presented. Moreover, implementation, realization, and performance analysis and evaluation of the mapped designs are included.

MorphoSys reconfigurable hardware for cryptography: the twofish case

This paper presents the mapping and performance analysis of the Twofish algorithm on MorphoSys. MorphoSys is a reconfigurable architecture that can provide high performance compared to custom hardware and yet preserves a level of flexibility compared to general-purpose processors. With today’s high demand for secure data transfer mediums including wired and wireless networks, there is a growing demand for real-time implementation of cryptographic algorithms. The choice of the Twofish algorithm, one of the five AES finalists, is because it is computationally intensive algorithm. It requires lookup tables, logical and arithmetic computations that stipulate high flexibility and performance. So it is a perfect algorithm to be mapped in order to evaluate such hardware.

Reconfigurable Platform Evaluation Through Application Mapping And Performance Analysis

The area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse grain hardware. Since the field is still in its infancy, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents analysis of the advanced encryption standard (Rijndael), which is then implemented on a coarse grain reconfigurable platform (MorphoSys). We provide details of mapping Rijndael and present an analysis to highlight the apparent bottlenecks. We suggest methods of upgrading and enhancing the MorphoSys hardware accordingly

FIR filter mapping and performance analysis on MorphoSys

This paper introduces reconfigurable computing (RC) and specifically chooses one of the prototypes in this field, MorphoSys (M1) from UCI. A mapping of the FIR filter algorithm onto this hardware is proposed. A performance analysis study of the M1 RC is also presented to evaluate the efficiency of the FIR execution on the M1 system. An example (8-tap FIR filter on an 8/spl times/8 RC array M1) was run, to validate our results, using the MorphoSys mULATE program, which simulates MorphoSys operation.

Analog computer simulation using spreadsheets

In this paper, a spreadsheet simulation of an analog computer is presented. Each available module on the analog computer is simulated using the mathematical functions of the Excel spreadsheet. These modules are connected via a connecting method representing the interrelationship that exists among the various blocks of a system. This tool provides a simple way to compose the overall block diagram of a given system by connecting its blocks according to the signal flow. As a result, the performance of each component of the system can be observed and tested using the spreadsheet chart facilities. Examples are given for illustration, and comparison with other simulation tools is presented.

Fuzzy logic arbiters for multiple-bus multiprocessor systems

This paper describes and evaluates the use of fuzzy logic arbiters for multiple-bus shared memory multiprocessor system. Multiple-bus systems allow multiple and simultaneous bus transfer in addition to a high degree of fault tolerance. In such systems, arbiters are used to resolve conflicts to system resources, which are the shared memory modules and the buses. Typically, these conflicts are resolved by using two-stage arbitration schemes that employ policies such as random choice, daisy chaining, round-robin, etc. A new way of implementing these arbiters is the use of fuzzy logic to resolve resource request conflicts based on the system state and performance variables. This paper describes a new technique for implementation of fuzzy logic in the system arbiters and presents a simulation program that evaluates the system performance. The program is coded in such a way as to accommodate any arbitration scheme, from which the fixed priority and fuzzy priority have been implemented. Parameters affecting multiple-bus system performance are considered and used as inputs to the fuzzy arbiters. The inputs are fuzzified by using appropriate membership functions, and rules have been defined in such a way as to increase and distribute evenly the acceptance probability of each processor in the system. Results from the simulation program using a prioritized arbitration scheme are compared against other published results and show very close agreement. Furthermore, results show an increase in the acceptance probability of the processors using fuzzy arbiters.