Hassan Ezzaidi

Wind speed sensorless maximum power point tracking control of variable speed wind energy conversion systems

A maximum power point tracking (MPPT) controller for variable speed wind energy conversion system (WECS) is proposed. The proposed method, without requiring the knowledge of wind speed, air density or turbine parameters, generates at its output the optimum speed command for speed control loop of rotor flux oriented vector controlled machine side converter control system using only the instantaneous active power as its input. The optimum speed commands which enable the WE to track peak power points are generated in accordance with the variation of the active power output due to the change in the command speed generated by the controller. The concept is analyzed in a direct drive variable speed permanent magnet synchronous generator (PMSG) WECS with back-to-back IGBT frequency converter. Vector control of the grid side converter is realized in the grid voltage vector reference frame. Simulation is carried out in order to verify the performance of the proposed controller.

FPGA-implementation of a sequential adaptive noise canceller using Xilinx System Generator

This paper presents a sequential architecture of a pipelined LMS-based adaptive noise cancellation to remove the power-line interference (50/60 Hz) from electrocardiogram (ECG). This architecture is implemented on on FPGA using XUP Virtex-II Pro development board and Xilinx System Generator (XSG). The proposed architecture was evaluated using real ECG signals from the MIT-BIH database. Hardware requirement of this adaptive noise canceller is presented for various filter lengths.

Artificial neural network-based maximum power point tracking control for variable speed wind energy conversion systems

A new maximum power point tracking (MPPT) controller using artificial neural networks (ANN) for variable speed wind energy conversion system (WECS) is proposed. The algorithm uses Jordan recurrent ANN and is trained online using back propagation. The inputs to the networks are the instantaneous output power, maximum output power, rotor speed and wind speed, and the output is the rotor speed command signal for the WECS. The network output after a time step delay is used as the feed-back signal completing the Jordan recurrent ANN. Simulation is carried out in order to verify the performance of the proposed algorithm.

FPGA-Implementation of Discrete Wavelet Transform with Application to Signal Denoising

This paper presents new architectures for real-time implementation of the forward/inverse discrete wavelet transforms and their application to signal denoising. The proposed real-time wavelet transform algorithms present the advantage to ensure perfect reconstruction by equalizing the filter path delays. The real-time signal denoising algorithm is based on the equalized filter paths wavelet shrinkage, where the noise level is estimated using only few samples. Different architectures of these algorithms are implemented on FPGA using Xilinx System Generator for DSP and XUP Virtex-II Pro development board. These architectures are evaluated and compared in terms of reconstruction error, denoising performance and resource utilization.

FPGA-Implementation of Parallel and Sequential Architectures for Adaptive Noise Cancelation

This paper presents a FPGA-based rapid prototyping of an adaptive noise canceller (ANC) using XUP Virtex-II Pro development board and Xilinx System Generator. New parallel and sequential architectures of the ANC are proposed and successfully applied to remove noise from electrocardiogram and speech signals. The pipelined architecture were evaluated and compared to existing high-speed systems using objective measurement tests. By providing comparable filtering performances that of the parallel architectures, the proposed sequential system required fewer material resources.

Pitch and MFCC dependent GMM models for speaker identification systems

Recently, we proposed an approach to speaker identification which jointly exploits vocal tract and glottis source information. The approach synchronously takes into account the correlation between the two sources of information. The proposed theoretical model, which uses a joint law, is presented. Some restrictions and simplifications are taken into account to show the significance of this approach in practical way. The fundamental frequency and MFCCs (Mel frequency cepstrum coefficients) are used to represent the information of the source and the vocal tract, respectively. The probability density of the source, in particular, was considered to obey a uniform law. Tests were carried out with only female speakers from a speech telephony database (SPIDRE) recorded from various telephone handsets. It is proposed to model the source information by a Gaussian mixture model (GMM) rather than the uniform probabilistic model. Tests were extended to all speakers of the SPIDRE database; four systems were proposed and compared. The first is a baseline system based on the MFCC and does not use any information from the source. The second examines only the voiced segments of the vocal signal. The last two relate to the suggested approaches according to the two techniques. The source information is found to follow a normal distribution in one technique and a log normal distribution in the other. With the proposed approach, the gain in performance is 10.5% for women, 7% for men and 8% for all speakers.

FPGA-implementation of wavelet-based denoising technique to remove power-line interference from ECG signal

This paper presents a real-time implementation on FPGA of a wavelet-based denoising technique applied to remove power-line interference from ECG signal. The soft-threshold is applied to the wavelet coefficients using the universal threshold estimated in the subband that includes the power-line frequency response. This real-time architecture presents two characteristics: 1) equalization of the filter path delays, and 2) estimation of the noise level from only a few samples. Experimental results show that the proposed architecture remove efficiently the power-line interference from ECG signal.

A Smart Safety Helmet using IMU and EEG sensors for worker fatigue detection

It is known that head gesture and brain activity can reflect some human behaviors related to a risk of accident when using machine-tools. The research presented in this paper aims at reducing the risk of injury and thus increase worker safety. Instead of using camera, this paper presents a Smart Safety Helmet (SSH) in order to track the head gestures and the brain activity of the worker to recognize anomalous behavior. Information extracted from SSH is used for computing risk of an accident (a safety level) for preventing and reducing injuries or accidents. The SSH system is an inexpensive, non-intrusive, non-invasive, and non-vision-based system, which consists of an Inertial Measurement Unit (IMU) and dry EEG electrodes. A haptic device, such as vibrotactile motor, is integrated to the helmet in order to alert the operator when computed risk level (fatigue, high stress or error) reaches a threshold. Once the risk level of accident breaks the threshold, a signal will be sent wirelessly to stop the relevant machine tool or process.

Real-time implementation of discrete wavelet transform on FPGA

This paper presents a real-time architecture for forward/inverse wavelet transforms that take into account the group delays of the used filters. The main idea is based on the equalization of the filter path delays. The perfect reconstruction of this architecture was evaluated for various data widths. This architecture was implemented on FPGA using XUP Virtex-II Pro development board.

Implementation of spectral subtraction method on FPGA using high-level programming tool

This paper presents a real-time architecture of spectral subtraction technique applied to speech enhancement. The proposed architecture is easily and quickly implemented on Field Programmable Gate Array (FPGA) using high-level programming tool in MATLAB/SIMULINK environment. Speech enhancement results obtained with fixed-point format implementation are compared to those obtained with the floating-point format one. The maximum operating frequency and resource utilization are presented for a Virtex-6 FPGA chip.