Hassan

MOS current mode circuits: analysis, design, and variability

The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-/spl mu/m CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.

Discrete cooperative particle swarm optimization for FPGA placement

Particle swarm optimization (PSO) is a stochastic optimization technique that has been inspired by the movement of birds. On the other hand, the placement problem in field programmable gate arrays (FPGAs) is crucial to achieve the best performance. Simulated annealing algorithms have been widely used to solve the FPGA placement problem. In this paper, a discrete PSO (DPSO) version is applied to the FPGA placement problem to find the optimum logic blocks and IO pins locations in order to minimize the total wire-length. Moreover, a co-operative version of the DPSO (DCPSO) is also proposed for the FPGA placement problem. The problem is entirely solved in the discrete search space and the proposed implementation is applied to several well-known FPGA benchmarks with different dimensionalities. The results are compared to those obtained by the academic versatile place and route (VPR) placement tool, which is based on simulated annealing. Results show that both the DPSO and DCPSO outperform the VPR tool for small and medium-sized problems, with DCPSO having a slight edge over the DPSO technique. For higher-dimensionality problems, the algorithms proposed provide very close results to those achieved by VPR.

Impact of technology scaling on RF CMOS

Inspired by the huge improvement in the RF properties of CMOS, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of the CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects, is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Using the BSIM4 model it is found that future CMOS technologies have high prospects in the RF industry.

Impact of technology scaling and process variations on RF CMOS devices

Inspired by the huge improvement in the RF properties of CMOS devices, RF designers are invading the wireless market with all-CMOS RF transceivers and system-on-chip implementations. In this work, the impact of technology scaling on the RF properties of CMOS; frequency properties, noise performance, linearity, stability, and non-quasi static effects is investigated to provide RF designers with an insight to the capabilities of future CMOS technologies. Moreover, the RF frequency performance of CMOS is investigated under the influence of process variations for different CMOS generations. Using the BSIM4 model, it is found that future CMOS technologies have high prospects in the RF industry and will continue challenging other technologies in the RF domain to be the dominant technology for RF transceivers and system-on-chip implementations.

Activity Packing in FPGAs for Leakage Power Reduction

In this paper, two packing algorithms for the detection of activity profiles in MTCMOS-based FPGA structures are proposed for leakage power mitigation. The first algorithm is a connection-based packing technique by which the proximity of the logic blocks is accounted for, and the second algorithm is a logic-based packing approach by which the weighted Hamming distance between the block activities is considered. After both algorithms are analyzed, they are applied to a number of FGPA benchmarks for verification. Once the activity profiles are realized, sleep transistors are carefully positioned to contain the clustered blocks that share similar activity profiles. Finally, the percentage of the leakage power savings for each of the two algorithms is evaluated.

MOS current mode logic: design, optimization, and variability

An automated optimization-based design strategy for 2-level MOS current mode logic (MCML) circuits is proposed to overcome the complexities of the design process. The methodology minimizes the power dissipation while satisfying the performance criteria. Moreover, environmental and process variations modeling are included in the design strategy. The impact of these variations on MCML performance as technology scales is also presented. In addition, design tips based on analytic formulation are presented for MCML designers. The proposed methodology is tested on several benchmarks belonging to optical communication and high-speed microprocessor applications built in a CMOS 0.18/spl mu/m process, at which the average error is within 7% between our formulation and HSPICE.

Discrete and continuous particle swarm optimization for FPGA placement

This paper proposes the use of a particle swarm optimization algorithm to the Field Programmable Gate Arrays (FPGA) placement problem. Two different versions of the particle swarm optimization algorithm are proposed. The first is a discrete version that solves the FPGA placement problem entirely in the discrete domain, while the second version is continuous in nature. Both versions are applied to several well-known FPGA benchmarks and the results are compared to those obtained by an academic placement tool that is based on adaptive simulated annealing. Results show that the proposed methods are competitive for small and medium-sized problems. For large-sized problems, the proposed methods provide very close results.

Input Vector Reordering for Leakage Power Reduction in FPGAs

In this paper, a leakage power reduction technique for field-programmable gate arrays (FPGAs) is proposed based on the state dependency property of leakage power. A pin reordering algorithm is proposed, where the subthreshold and gate leakage power components are taken into consideration to find the lowest leakage state for the FPGA pass-transistor multiplexers in the logic and routing resources without incurring any physical or performance penalties. The newly developed methodology is applied to several FPGA benchmarks, and an average leakage savings of 50.3% is achieved in a 90-nm CMOS process. Moreover, a modified version of the methodology is implemented to improve the performance of the final design, and again, considerable leakage power savings are achieved. Furthermore, the methodology is extended to find the lowest leakage states for several future predictive Berkeley CMOS technologies.

Analysis and design of low-power multi-threshold MCML

Multi-threshold MOS current mode logic (MTMCML) is a natural evolution for MCML that offers power saving through supply voltage reduction while retaining the same performance. In this work, analytical formulation based on the BSIM3v3 model is proposed for MTMCML with error within 10% compared to HSPICE. The formulation helps designers to efficiently design MTMCML circuits without undergoing the time-consuming HSPICE simulations. Furthermore, it provides design guidelines and aids for designers to fully understand the different tradeoffs in MTMCML design. In addition, the analysis is extended to study the impact of technology scaling and parameter variations on MTMCML. It is shown that the worst case variation in the minimum supply voltage of MTMCML is 1.16%, thus suggesting maximal power saving.

Design and optimization of MOS current mode logic for parameter variations

An automated optimization-based design strategy is proposed for single-level MOS Current Mode Logic (MCML) gates to overcome the complexities of the gate design procedure. The proposed design methodology determines the values of the design variables that achieve the minimum power dissipation point while attaining the required performance. The proposed design methodology has the advantage of speed, accuracy, and ability to include a large number of parameters in the design problem. Moreover, a formulation for the impact of parameter variations on the MCML gate performance is presented. The proposed strategy is used to design two popular circuits, namely; the ring oscillator and clock distribution network drivers with an average error from the required performance within 8%. The dependence of the gate parameters on parameter variations is used with the design methodology to redesign the same circuits while considering parameter variations. Furthermore, the impact of parameter variations as the technology scales down is investigated.