Hassan M. Ahmed

Efficient elementary function generation with multipliers

Virtually all numerical techniques for elementary function generation share the common property of avoiding multiplication by iteratively performing shift operations. However, with the advent of VLSI, multiplier economics are considerably less formidable than before. The author proposes combining multipliers with these multiplication-free algorithms to construct fast methods of elementary function generation. He demonstrates the idea by combining multipliers with the CORDIC algorithm to achieve fast vector rotation.<<ETX>>

Directions in DSP processors

The evolution of single-chip digital signal-processor (DSP) architectures is discussed. It is argued that multiple arithmetic units and functionally enhanced arithmetic units are promising directions for further evolution of the datapath architecture. Candidate structures are defined, and the operation of popular DSP benchmarks on these structures is demonstrated. >

Calculation of Lyapunov exponents through nonlinear adaptive filters

The authors present a novel approach, using nonlinear adaptive filter, to model, filter, and predict chaotic time series. Lyapunov exponents can be estimated from the prediction error growth rate of such filters. The technique is very effective for detecting and quantifying low-dimensional chaos. The technique performs accurately even under noisy environments. Measurement noise and catastrophic noise are both handled equally well in this technique and do not hinder the estimate of the Lyapunov exponent since they are adequately filtered. The authors have demonstrated their technique with Henon and logistic maps. They have also presented a more reliable and accurate algorithm for estimation of Lyapunov exponents from finite and noisy time series data for applications in econometrics and other fields where large numbers of data points are not available.<<ETX>>

A VLSI array CORDIC architecture

Use of the CORDIC (COordinate Rotation DIgital Computer) algorithm has been proposed for signal processing applications, since it has been shown that many DSP algorithms are fundamentally described by generalized rotations. However, the iterative nature of CORDIC has diminished its utility in high-speed real-time signal processing applications. The authors propose an array architecture for VLSI implementation of the CORDIC algorithm that aims to circumvent this shortcoming. The size and speed of the structure is compared with those of array multiplier and array divider structures. It is shown that the array CORDIC, while consuming a larger absolute real estate than these other structures, provides a better speed/area tradeoff as well as a rich set of elementary functions.<<ETX>>

Nadine-a feedforward neural network for arbitrary nonlinear time series

It is shown that Madaline networks applied to the modeling of time series realize a constrained Volterra series because of the fixed nature of the nonlinearity. The authors introduce a novel feedforward structure, named Nadine, that can model arbitrary Volterra series and hence arbitrary, analytic nonlinearities with memory. Nadine can be realized using layers of adaptive linear combiners in which the outputs of one layer are used as the weights rather than the activities of the next layer. This structure admits local adaptation of the linear combiners, making it possible to implement backpropagation-style learning without actually propagating adaptation information between the layers. Nadine is therefore very modular, easy to implement, and readily extendible. High-order neural networks and polynomial discriminant-based methods are the special cases of Nadine which can now be implemented modularly without involving preprocessing.<<ETX>>

A Custom VLSI Chip Set for Digital Signal Processing in High-Speed Voiceband Modems

Systems modems intended for use in relatively large private networks are characterized by high performance, reliability and flexibility to support network management, and multiple modes of operation and user features. This paper describes a programmable digital signal processor which is teamed with a 16-bit microprocessor in a dual processor architecture satisfying the requirements of high-speed voiceband systems modems. The architecture of the two custom integrated circuits which form the basis of the signal processor is presented. This processor has novel arithmetic, data structure address generation, and program flow-control capabilities, which result in a high utilization of the arithmetic unit and a low program overhead for housekeeping tasks. Some of these features are illustrated by programming examples.

Fast learning neural networks using transform domain LMS structure

Transform domain adaptive filtering, which uses orthogonal transforms to partially uncorrelate the colored input, thus reducing the eigenvalue spread, is extended to the nonlinear domain and used as the basis of a learning algorithm for neural networks. Computer simulations show that this neural structure learns much faster than least-mean-square-based structure.<<ETX>>

Adaptive bilinear inverse filtering

A parsimonious adaptive nonlinear filtering structure based on bilinear models is presented. A state-dependent embedding for developing nonlinear filters is presented. It is used to develop a computationally efficient bilinear adaptive filter which requires only local adaptation. Modularity and local connectivity make the structure amenable to VLSI implementation. In contrast to previous input-output pair (system identification) frameworks, an inverse filtering problem is considered where only output is observable. The adaptation is shown to be dependent on both past and present gradients.<<ETX>>

A custom VLSI architecture for the CCITT wideband coding standard

A custom VLSI architecture for implementing the CCITT G.722 64-kb/s (7-kHz) wideband audio coding standard is presented. By tailoring the architecture to the algorithm, an architecture was designed that is capable of processing a full duplex channel in less than 625 cycles. That is 71-73% less cycles than are required by the reported general-purpose DSP implementations. In a 1.5- mu technology with a 100-ns cycle time, it is estimated that the architecture would consume 95000 mL/sup 2/ of silicon and support two full duplex channels on a single chip. The authors wrote a behavioral simulation of the architecture and its implicit microcode. This simulates the architectures behavior at the bit level. The simulation passes the CCITT G.722 test vectors, demonstrating that the implementation conforms to the standard. >

Fast recursive adaptation for nonlinear filters

A new recursive procedure is presented for developing fast algorithms for nonlinear adaptive filters. Fast recursive adaptation is achieved at a computational cost comparable to simple stochastic gradient algorithms. Successive linearization is shown to be an adequate approximation procedure for developing a general class of nonlinear adaptive filters.<<ETX>>