Hau T. Ngo

A pipelined architecture for real-time correction of barrel distortion in wide-angle camera images

An efficient pipelined architecture for the real-time correction of barrel distortion in wide-angle camera images is presented in this paper. The distortion correction model is based on least-squares estimation to correct the nonlinear distortion in images. The model parameters include the expanded/corrected image size, the back-mapping coefficients, distortion center, and corrected center. The coordinate rotation digital computer (CORDIC) based hardware design is suitable for an input image size of 1028/spl times/1028 pixels and is pipelined to operate at a clock frequency of 40 MHz. The VLSI system will facilitate the use of a dedicated hardware that could be mounted along with the camera unit.

A multisensor image fusion and enhancement system for assisting drivers in poor lighting conditions

A system of multisensor image fusion and enhancement for visibility improvement is proposed in this paper for helping drivers driving at night or under bad weather conditions. Video stream captured by a CCD camera is enhanced, then aligned and fused with another stream captured by a thermal camera to improve the visibility of roads in extremely low lighting conditions. A nonlinear image enhancement technique capable of dynamic range compression and contrast enhancement is developed to enhance the visible images prior to fusion. The thermal image and the enhanced visible image are then aligned based on prior information obtained on image registration process. Pixel-level multiresolution based image fusion method is applied to merge source images. After image fusion, a color restoration is performed on fused images with the chromatic information of visible images. The entire image processing and analysis system is being installed in an FPGA environment. Preliminary results obtained in various experiments conducted with the proposed system are encouraging

A Visibility Improvement System for Low Vision Drivers by Nonlinear Enhancement of Fused Visible and Infrared Video

Development of a visibility improvement system for helping drivers with poor vision during night and bad weather conditions is proposed in this paper. Video streams captured by a CCD camera and an infrared camera are registered and fused to obtain image details in extremely low lighting conditions. A novel image enhancement technique employing a nonlinear expansion function is developed for enhancing the fused images. The slope characteristics of the expansion function at an individual pixel location is based on the statistical properties of its neighborhood pixels. The expansion function is also capable of reducing the intensity of the overly bright image regions due to the presence of head lights from vehicles in opposite direction. The enhanced video stream is then subjected to a color restoration process to introduce natural color using the color information gathered from the CCD camera image. The entire image processing and analysis system is being installed in an FPGA environment for performing the processing in real-time. The processed video stream is displayed on a Head-Up Display located directly in front of the driver to assist him/her to drive safely in poor visibility environments. Preliminary results obtained in various experiments conducted with the proposed system are encouraging.

A flexible and efficient hardware architecture for real-time face recognition based on eigenface

We describe a flexible and efficient multilane architecture for real-time face recognition system based on modular principal component analysis (PCA) method in a field programmable gate array (FPGA) environment. We have shown in Gottumukkal R., and Asan K.V., (2004) that modular PCA improves the accuracy of face recognition when the face images have varying expression and illumination. The flexible and parallel architecture design consists of multiple processing elements to operate on predefined regions of a face image. Each processing element is also parallelized with multiple pipelined paths/lanes to simultaneously compute weight vectors of the non-overlapping region, hence called multilane architecture. The architecture is able to recognize a face image from a database of 1000 face images in 11ms.

Multi-lane architecture for eigenface based real-time face recognition

Abstract The concept of simultaneously processing different non-overlapping spatial regions of an image and combining the results to obtain a final image is used in this paper. We apply this concept to the domain of face recognition using Principal Component Analysis (PCA). We have shown in [1] that modular PCA improves the accuracy of face recognition when the face images have varying expression and illumination. In this work we design and implement the modular PCA algorithm for face recognition in a Field Programmable Gate Array (FPGA) environment. Since modular PCA processes non-overlapping regions of a face image to produce weight vectors, we design a parallel architecture where each parallel path has a processing element to process a predefined region of a face image. Each processing element computes a weight vector from a face image region and pre-computed eigenvectors; hence the processing element is also parallelized where each path works on one eigenvector and the face image region to compute one element in the weight vector. Each of these paths is pipelined to process the pixels from the face image region and corresponding elements from the eigenvectors in a faster manner. We name this design having pipelined parallel paths as multi-lane architecture. The architecture is able to recognize a face image from a database of 1000 face images in 11 ms.

An efficient VLSI architecture for 2-D convolution with quadrant symmetric kernels

A high performance digital architecture for computing 2D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously for computing the partial products of the convolution sum. A novel data handling strategy to identify the pixels to be fed to different processing elements helps reducing the data storage requirements in the circuitry. The new design results in 75% reduction in multipliers and 50% reduction in adders when compared with the conventional systolic architecture. The proposed architecture design is capable of performing convolution operations with 14/spl times/14 kernel at a rate of 57 1024/spl times/1024 frames per second in a Xilinx s Virtex 2v2000ff896-4 FPGA.

Design of an efficient multiplier-less architecture for multi-dimensional convolution

Design of a hardware efficient multiplier-less architecture for the computation of multi-dimensional convolution is presented in this paper. The new architecture performs computations in the logarithmic domain by utilizing novel multiplier-less log2 and inverse-log2 modules. An effective data handling strategy is developed in conjunction with the logarithmic modules to eliminate the necessity of multipliers in the architecture. The proposed approach reduces hardware resources significantly compared to other approaches while it still maintains a high degree of accuracy. The architecture is developed as a combined systolic-pipelined design that produces an output in every clock cycle after the initial latency of the system. The architecture is capable of operating with a high speed clock frequency of 99 MHz based on Xilinx’s Virtex II 2v2000ff896-4 FPGA and the throughput of the system is observed as 99 MOPS (million outputs per second).

Real-time video surveillance on an embedded, programmable platform

In this work, a hardware-software co-design is proposed to effectively utilize FPGA resources for a prototype of an automated video surveillance system on a programmable platform. Time-critical steps of a foreground object detection algorithm are designed and implemented in the FPGAs logic elements to maximize parallel processing. Other non time-critical tasks are achieved by executing a high level language program on an embedded Nios-II processor. Custom and parallel processing modules are integrated into the video processing chain by a streaming protocol that aggressively utilizes on-chip memory to increase the throughput of the system. A data forwarding technique is incorporated with an on-chip buffering scheme to reduce computations and resources in the window-based operations. Other data control interfaces are achieved by software drivers that communicate with hardware controllers using Alteras Memory-Mapped protocol. The proposed prototype has demonstrated real-time processing capability that outperforms other implementations.

Resource-aware architecture design and implementation of hough transform for a real-time iris boundary detection system

In this paper, a resource efficient architecture design for the circular Hough transform based on Field Programmable Gate Array (FPGA) technology is presented. The circular Hough transform is implemented to detect iris boundary in a binary edge image. A novel modular design is proposed to reduce the required memory space by 93% compared to the direct implementation while maintaining a high detection rate over 92%. The parallel-pipelined implementation of the proposed architecture demonstrates a high speed processing capability that is suitable to support real-time iris recognition in resource constrained systems. Therefore, the proposed technology can be used in portable consumer devices such as mobile phones and tablets where iris recognition application is involved.

An area efficient modular architecture for real- time detection of multiple faces in video stream

Design of an efficient modular architecture for detection of multiple faces in video stream is presented in this paper. Face detection is the first step in many surveillance and security applications such as face recognition, face authentication for banking and security access control, monitoring and tracking, etc. The algorithm used for this hardware design is the Viola-Jones algorithm, which has proven to be very effective and fast. The hardware design employs a modular approach in an efficient memory management strategy for this memory-intensive application. The proposed design is targeted for a low-cost FPGA prototype board from Altera (DE2 board) for a cost-effective face detection system. The proposed approach utilizes the on-chip memory module to reduce accesses to external memory chip for improved performance in the application.