Hazem A. Ahmed

Low energy high speed reed-solomon decoder using two parallel modified evaluator Inversionless Berlekamp-Massey

This paper proposes a low power high throughput Reed Solomon decoder designed optimally for handheld devices under the DVB-H standard. This architecture based on Decomposed Inversionless Berlekamp-Massey Algorithm (DiBM), where the error locator and evaluator polynomial can be computed serially. In the proposed architecture, a new scheduling of 6 Finite Field Multipliers (FFMs) is used to calculate the error locator polynomial in a two parallel way and these multipliers are reused to calculate the error evaluator polynomial in a novel architecture called two parallel modified evaluator decomposed inversionless Berlekamp-Massey (MEDiBM) to achieve low energy. This architecture is tested in a pipelined two parallel decoder. This decoder has been implemented by 0:13μm CMOS IBM standard cells for RS(204; 188) and gave gate count of 33K and area of 1:06mm2. Simulation results show this approach can work successfully at the data rate 100Mbps with power dissipation of 0:266mW.

A low energy high speed Reed-Solomon decoder using Decomposed Inversionless Berlekamp-Massey Algorithm

This paper proposes an area efficient, low energy, high speed pipelined architecture for a Reed-Solomon decoder based on Decomposed Inversionless Berlekamp-Massey Algorithm, where the error locator and evaluator polynomial can be computed serially. In the proposed architecture, a new scheduling of t Finite Field Multipliers (FFMs) is used to calculate the error locator and evaluator polynomials to achieve a good balance between area, latency, and throughput. This architecture is tested in two different decoders. The first one is a pipelined two parallel decoder, as two parallel syndrome and two parallel Chien search are used. The second one is a conventional pipelined decoder, as conventional syndrome and Chien search are used. Both decoders have been implemented by 0.13µm CMOS IBM standard cells. The two parallel RS(255, 239) decoder has gate count of 37.6K and area of 1.18mm2, simulation results show this approach can work successfully at the data rate 7.4Gbps and the power dissipation is 50mW. The conventional RS(255, 239) decoder has gate count of 30.7K and area of 0.99mm2. Simulation results show this approach can work successfully at the data rate 4.85Gbps and the power dissipation is 29.28mW.

Maximum Likelihood decoding for non-synchronized UHF RFID tags

In Radio Frequency Identification (RFID) systems, when multiple tags reply at the same slot, collision occurs. The tags reply are with different data and also different rates. The rate tolerance between the tags reply reaches to +/-22% of the nominal value of the rate which plays a significant role for the stability and the efficiency of RFID systems. This variation in the tags reply rates inhibit to use the ML receiver which is very sensitive to the rate variation between collided replies. This paper focuses on decoding the collided tags with different rates in the RFID systems using Maximum Likelihood (ML) receiver. A new algorithm is proposed to make the ML receiver is insensitive the rate tolerance between the tags reply. The simulations show that the dual receive antennas ML receiver that is used to recover two collided tags over Rayleigh channel is not affected by the rate tolerance. The receiver performance is compared with the previous proposed dual antenna receivers, Minimum Mean Square Error (MMSE), Zero Forcing (ZF), and Ordered SUccessive Cancellation (OSUC). The proposed receiver outperforms the other types of receivers as it has the largest diversity gain.

A closed form solution for frame slotted ALOHA utilizing time and multiple collision recovery coefficients

Minimizing the reading time of large tag populations is a critical issue in Radio Frequency Identification (RFID) systems. The usual approach to reduce the reading time is to select the frame size attaining the highest throughput per frame. Previous studies have focused on conventional frame length calculations. In such systems, only the answer of a single tag is considered as a successful slot. If multiple tags respond simultaneously within a slot a collision occurs. Then, all tags within this slot are discarded. However, modern system have the capability of converting part of the collided slots into successful slots. This is called Collision Recovery. Moreover, modern RFID readers have the ability to identify the type of the slot (successful, collided, or empty). Then, the readers are able to terminate the slot earlier when they recognizes that there is no tag reply. This system is called a time aware system. Recent studies focused on calculating the optimal frame length taking into consideration the time aware and the collision recovery properties. However, these studies have assumed constant collision recovery probability coefficients, i.e. the probability to recover one tag from i collided tags is constant, regardless of the number of collided tags i. Moreover, they proposed only numerical solutions for the optimum frame length. In this paper we propose a novel closed form solution for the optimal Frame Slotted ALOHA (FSA) frame length. The novel solution considers the multiple collision recovery probability coefficients, and the different slot durations. Timing comparisons are presented in the simulation results to show the reading time reduction using the proposed frame length compared to other the state-of- the-art algorithms.

Performance evaluation of rate estimation for UHF RFID systems

This paper focuses on the rate estimation in radio frequency identification (RFID) reader receivers, which plays a significant role for the stability and the efficiency of RFID systems. RFID readers have to estimate the rate of the tag reply, i.e. the so-called backscatter link frequency (BLF). According to the focused EPCglobal Class-1 Gen-2 standard, the BLF can have a variation of up to +/−22%. Most literature uses time domain algorithms to estimate this BLF. However, the proposed techniques are not suitable to estimate the rate when multiple tags reply simultaneously to the reader. In case of such tag collision we utilized the frequency domain representation of the replies to estimate the BLF. The performance is tested with different rates and the both supported modulation techniques, i.e. FM0 and Miller. Simulation results show the high performance of utilizing the Fast Fourier Transform (FFT) and Multiple SIgnal Classification (MUSIC) algorithm for estimating the BLF. This especially holds in case of collisions that cannot be easily estimated by means of time domain algorithms.

Low-energy configurable syndrome/chien search multi-channel Reed Solomon decoder

This paper presents a low-energy configurable syndrome/chien search pipelined Reed-Solomon RS (255; 239) decoder architecture using Euclidean algorithm. The configurable structure enables the syndrome and Chien search blocks to work either in serial mode which needs 255 clock cycle to finish, or in two parallel mode which needs 128 clock cycle to finish. The Euclidean algorithm block can be shared with 8 or 16 channels based on the required rate per channel. In serial mode, the configurable cells enable the Euclidean algorithm block to be shared between 16 channels each channel takes rate up to 4 Gbps. In two parallel mode, the configurable cells enable the Euclidean algorithm block to be shared between 8 channels each channel takes rate up to 8 Gbps with latency reduction of 47% and power reduction of 27% relative to using two serial channels in parallel. The 16 channel RS (255; 239) decoder has been implemented by 0.13µm CMOS IBM standard cells with a gate count of 200K and area of 20mm2, simulation results show this approach can work successfully at the data rate 64Gbps