He Tang

ESD-Protected Power Amplifier Design in CMOS for Highly Reliable RF ICs

Electrostatic discharge (ESD) failure is a major reliability problem, and ESD protection is an emerging design challenge for radio-frequency (RF) integrated circuits demanding extremely high reliability for wireless applications in harsh environments. This paper reports the design and optimization of a 5-kV ESD-protected 2.4-GHz power amplifier (PA) circuit in a 0.18-μm RFCMOS technology. A new mixed-mode ESD simulation-design method and an accurate RF ESD characterization technique are used to minimize the inevitable ESD-induced parasitic effects, which can significantly degrade PA circuit performance. A novel ESD-aware PA design technique is utilized to optimize whole-chip ESD+PA performance. Experiments show that conventional ESD protection can seriously affect the PA circuit, while optimized ESD protection may resolve such a problem. The optimized ESD-protected PA circuit achieves good whole-chip performance, including 5-kV ESD protection, a linear output of 13.5 dBm, a gain of 20.2 dB, and a power-added efficiency of ~ 18%, all favorable in the same design category.

A Whole-Chip ESD-Protected 0.14-pJ/p-mV 3.1–10.6-GHz Impulse-Radio UWB Transmitter in 0.18-

This paper presents the design of a low-power single-full-band (3.1-10.6 GHz) noncarrier impulse-radio ultra-wideband (UWB) transmitter (TX) implemented in a commercial 0.18-μm CMOS technology. This UWB TX features fifth-order Gaussian derivative pulse shaping, integrated binary phase-shift keying modulation and 2.5-kV whole-chip electrostatic discharge (ESD) protection. Measurement shows full function with a very small die size of 0.25 mm2, extremely low power consumption of 0.14 pJ/p-mV, and an ultrashort pulsewidth of 394 ps. This ESD-protected UWB TX has the potential to support wireless streaming for gigabit/second applications.

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This paper presents a single-chip ultralow power programmable Gaussian pulse generator (PG) designed and implemented in the 90-nm CMOS for 3.1-10.6 GHz full-band impulse-radio ultrawideband (UWB) transmitters. Measurement shows that this novel simple two-inverter-based PG achieves the lowest reported power dissipation of merely 1.8 pJ/pulse with a 100-MHz pulse-repeating frequency at 1-V supply, extremely short and programmable pulsewidth ranging from 150 to 350 ps while covering the full 3.1-10.6 GHz UWB spectrum, and a very small area of 0.0068 mm2. It supports up to 6 Gb/s data rate for UWB wireless streaming. A new Federal-CommunicationCommission-aware Gaussian PG design optimization method is discussed and verified experimentally.

CMOS

This paper reports design, analysis and optimization of a new low-parasitic, very-low-triggering-voltage dual-directional silicon-controlled rectifier (VLTdSCR) type electrostatic discharge (ESD) protection structure and its cross-coupling ultra-low-triggering ESD protection circuitry (CULTdSCR) implemented in a commercial 0.18 μm CMOS. Mixed-mode ESD simulation-design technique is used to verify the new embedded punch-through and gate cross-coupling ESD trigger-assisting techniques devised to achieve ultra-low ESD triggering for SCR-type ESD protection in CMOS. Experiment shows a record low ESD triggering voltage (Vt1) of 3.83 V, noise figure (NF) of 0.2 dB, parasitic ESD capacitance (CESD) of 150 fF and prompt response to very fast ESD pulses with rising time (tr) down to 100 pS. The new ESD design achieves a very high dual-directional charged device model (CDM) ESD protection capability of ~7 V/μ m2.

1.8 pJ/Pulse Programmable Gaussian Pulse Generator for Full-Band Noncarrier Impulse-UWB Transceivers in 90-nm CMOS

This paper reviews a systematic method for design and analysis of high-order Gaussian pulse generators (PG) for carrier-free impulse-radio ultra wideband (IR-UWB) transceivers, which enables to achieve PG performance optimization and FCC effective isotropic radiated power (EIRP) compliance simultaneously. The new FCC-EIRP-aware design method is verified experimentally using Gaussian PG circuits with different derivative orders designed in CMOS.

Design and Analysis of Low-Voltage Low-Parasitic ESD Protection for RF ICs in CMOS

This paper reports a new nanocrystal quantum-dot (NC-QD)-based tunable on-chip electrostatic discharge (ESD) protection mechanism and structures. Experiments validated the programmable ESD protection concept. Prototype structures achieved an adjustable ESD triggering voltage range of 2.5 V, very fast response to ESD transients of rising time tr ~ 100 ps and pulse duration td; ~ ns, ESD protection density of 25 mA/μm in human body model and 400 mA/μm in charged device model equivalent stressing, and a very low leakage current of Ileak ~ 15 pA. The NC-QD ESD protection concept can potentially be used to design field-programmable on-chip ESD protection circuitry for mixed-signal ICs in nanoscales.

FCC-EIRP-aware UWB pulse generator design approach (invited)

This letter reports the proof-of-concept results for the new nontraditional nanophase-switching electrostatic-discharge (ESD) protection mechanism and nanocrossbar ESD structures. Experiment shows good ESD switching and protection, i.e., a fast response of 100 ps, a ultralow leakage of 0.26 pA, and an ESD protection of >; 267 V/μm2. A new dispersed local ESD tunneling model is proposed, and heterogeneous complementary metal-oxide-semiconductor integration is developed.

Programmable On-Chip ESD Protection Using Nanocrystal Dots Mechanism and Structures

We report the first fuse-based field-dispensable electrostatic discharging (ESD) protection structure to eliminate the ESD-induced parasitics, hence, enable ultrahigh-speed ICs with robust ESD protection. Silicon results validate the new ESD protection concept for more than 20 Gb/s ICs in a 28-nm CMOS.

Novel Nanophase-Switching ESD Protection

Correlators play key roles in impulse radio ultrawideband (IR-UWB) transceivers. Multiplier-based correlator performs correlation-type demodulation in addition to select desired UWB signals by correlating incoming pulses with templates. This paper reports design and implementation of a fully integrated low-power broadband multiplier-based correlator for a 3.1-10.6-GHz fullband IR-UWB receiver in 0.18 μm CMOS that consists of a UWB multiplier core, two UWB pulse generators, single-ended-to-differential-ended converter, a first-order RC integrator with a 200-MHz bandwidth, and a buffer. Measurement results confirm desired correlation-type demodulation and correlation functions with a conversion gain of 11.03 dB, noise figure of 15.7 dB, very low power consumption of 52 mW and a 1-dB compression point of better than -0.8 dBm over a 7.5-GHz bandwidth.

Fuse-Based Field-Dispensable ESD Protection for Ultra-High-Speed ICs

This paper discusses a systematic study of electrostatic discharge (ESD) protection circuit co-design and analysis technique for high-frequency and high-speed ICs in 28 nm CMOS. The comprehensive ESD-IC co-design flow includes ESD device optimization and characterization, ESD behavioral modeling, backend interconnect characterization, parasitic ESD parameter extraction, ESD failure analysis and ESD co-design evaluation for ICs operating at up to 15 GHz and 40 Gbps. Ring oscillator, dummy I/O buffer and current mode logic (CML) circuits were used to demonstrate the co-design method. This practical ESD-IC co-design technique can be applied to high-performance, high-frequency and high-speed ICs.