He Weifeng

Efficient frame-level pipelined array architecture for full-search block-matching motion estimation

Motion estimation plays an important role in video compression to remove temporal redundancies between successive frames. An efficient frame-level pipelined FSBM (full-search block-matching) motion estimation systolic array architecture for the search range p=kN (k>1/2) is proposed. Design efforts are made to remove data broadcasting operations, to achieve 100% processor utilization and to reduce the hardware overhead while still keeping the scalability of the search range. It compares favorably with existing motion estimation architectures in terms of hardware cost, performance and complexity of architecture. As such, this architecture offers a feasible solution for digital TV and HDTV video picture formats.

Design and implementation of motion compensation for MPEG-4 AS profile streaming video decoding

This paper presents an efficient motion compensation architecture for MPEG-4 advanced simple profile at level 5 (ASP@L5) streaming video standard. A novel local memory storage scheme for motion vector prediction is proposed in the paper. In this scheme, local memory for storing differential data of motion information in video packet layer is avoided, and total memory access bandwidth is reduced 1/3. The motion compensation unit is implemented using 0.25μm 1-poly 5-metal CMOS technology, which occupies a silicon area of 1.35×1.35 mm2 and operates at 150MHz. Simulation result shows that it is capable of compensating AS profile sequences at ITU-601 resolution video in real time.This paper presents an efficient motion compensation architecture for MPEG-4 advanced simple profile at level 5 (ASP@L5) streaming video standard. A novel local memory storage scheme for motion vector prediction is proposed in the paper. In this scheme, local memory for storing differential data of motion information in video packet layer is avoided, and total memory access bandwidth is reduced 1/3. The motion compensation unit is implemented using 0.25mm 1-poly 5-metal CMOS technology, which occupies a silicon area of 1.35t1.35 mm2 and operates at 150MHz. Simulation result shows that it is capable of compensating AS profile sequences at ITU-601 resolution video in real time.

Implementation of half-pel motion estimation IP core for MPEG-4 ASP@L5 texture coding

An efficient fully pipelined parallel 1-D and 2-D mixed motion estimation array architecture for MPEG-4 ASP@L5 encoder is proposed in This work. Unlike most previously presented motion estimation processors, this design can deal with 8/spl times/ block and 16 /spl times/ 6 macroblock motion estimation with different searching ranges in full-pel and half-pel resolution. Experimental results show that it is able to estimate half-pel texture motion vectors of MPEG-4 AS Profile in ITU-R601 format in real-time at around 100MHz.