He-Yuan Lin

Algorithm/Architecture Co-Design of 3-D Spatio–Temporal Motion Estimation for Video Coding

This paper presents a new spatio-temporal motion estimation algorithm and its VLSI architecture for video coding based on algorithm and architecture co-design methodology. The algorithm consists of the new strategies of spatio-temporal motion vector prediction, modified one-at-a-time search scheme, and multiple update paths derived from optimization theory. The hardware specification is for high-definition video coding. We applied the ME algorithm to H.264 reference software. Our algorithm surpasses recently published research and achieves close performance to full search. The VLSI implementation proves the low cost feature of our algorithm. The algorithm and architecture co-design concept is highly emphasized in this paper. We provide some quantitative example to show the necessity of algorithm and architecture co-design

A motion-adaptive deinterlacer via hybrid motion detection and edge-pattern recognition

A novel motion-adaptive deinterlacing algorithm with edge-pattern recognition and hybrid motion detection is introduced. The great variety of video contents makes the processing of assorted motion, edges, textures, and the combination of them very difficult with a single algorithm. The edge-pattern recognition algorithm introduced in this paper exhibits the flexibility in processing both textures and edges which need to be separately accomplished by line average and edge-based line average before. Moreover, predicting the neighboring pixels for pattern analysis and interpolation further enhances the adaptability of the edge-pattern recognition unit when motion detection is incorporated. Our hybrid motion detection features accurate detection of fast and slow motion in interlaced video and also the motion with edges. Using only three fields for detection also renders higher temporal correlation for interpolation. The better performance of our deinterlacing algorithm with higher content-adaptability and less memory cost than the state-of-the-art 4-field motion detection algorithms can be seen from the subjective and objective experimental results of the CIF and PAL video sequences.

On the efficient algorithm/architecture co-exploration for complex video processing

Targeted for highly sophisticated visual signal processing, we introduce in this paper complexity metrics or measures of algorithms which featuring architectural information are feedback or back annotated in early design stages to facilitate concurrent exploration of both algorithmic and architectural optimizations. With application to 3D spatio-temporal motion estimation for video coding, we have demonstrated significant reduction in design cost while the algorithmic performance still surpasses recent published works and even full search under many circumstances. Moreover, we have also shown the importance and substantiality of this complexity analysis technique in the extraction of features common to various different de-interlacing algorithms adapted for versatile video content, in designing highly efficient reconfigurable video architectures. As such this novel algorithm/architecture co-exploration methodology forms the basis for dataflow models with more accurate software/hardware partitioning resulting in multi-million gate and/or instruction software simulation platforms and fast prototyping hardware platforms for the next generation electronic system level design of SoCpsilas.

A high-quality spatial-temporal content-adaptive deinterlacing algorithm

This paper introduced a spatial-temporal content- adaptive algorithm, which can precisely select an appropriate interpolation technique for high-quality deinterlacing according to the spectral, edge-oriented and statistical features of local video content. Our algorithm employs a linear-phase statistical- adaptive vertical-temporal filter to deal with generic video scenes and adopts a modified edge-based line-averaging interpolation to efficiently recover moving edges. In addition, annoying flickering artifacts are efficiently suppressed by a flickering detection and a field-averaging filter. As a result, our algorithm outperforms other non-motion compensated methods in terms of objective PSNR and reveals more impressive subjective visual quality.

Quantifying intrinsic parallelism via eigen-decomposition of dataflow graphs for algorithm/architecture co-exploration

Algorithmic complexity analysis and dataflow models play significant roles in the concurrent optimization of both algorithms and architectures, which is now a new design paradigm referred to as Algorithm/Architecture Co-exploration. One of the essential complexity metrics is the parallelism revealing the number of operations that can be concurrently executed. Inspired by the principle component analysis (PCA) capable of transforming random variables into uncorrelated ones and hence dependency analysis, this paper presents a systematic methodology for identifying independent operations in algorithms and hence quantifying the intrinsic degree of parallelism based on the dataflow modeling and subsequent eigen-decomposition of the dataflow graphs. Our quantified degree of parallelism is platform-independent and is capable of providing insight into architectural characteristics in early design stages. Starting from different dataflows derived from signal flow graphs in basic signal processing algorithms, the case study on DCT shows that our proposed method is capable of quantitatively characterizing the algorithmic parallelisms making possible the potentially facilitation of the design space exploration in early system design stages especially for parallel processing platforms.

Multiresolution-Based Texture Adaptive Algorithm for High-Quality Deinterlacing

This paper introduces a texture analysis mechanism utilizing multiresolution technique to reduce false motion detection and hence thoroughly improve the interpolation results for high-quality deinterlacing. Conventional motion-adaptive deinterlacing algorithm selects from inter-field and intra-field interpolations according to motion. Accurate determination of motion information is essential for this purpose. Fine textures, having high local pixel variation, tend to cause false detection of motion. Based on hierarchical wavelet analysis, this algorithm provides much better perceptual visual quality and considerably higher PSNR than other motion adaptive deinterlacers as shown. In addition, a recursive 3-field motion detection algorithm is also proposed to achieve better performance than the traditional 2-field motion detection algorithm with little memory overhead.

Multiresolution-based texture adaptive motion detection for de-interlacing

Motion-adaptive de-interlacing algorithm selects from inter-field and intra-field interpolations according to motion. Correct determination of motion information is essential for this purpose. Fine textures, having high local pixel variation, tend to cause false detection of motion. This paper proposed a texture detection mechanism utilizing multiresolution technique to improve the correctness of detection. A recursive 2-field algorithm is also proposed to reduce the memory cost in 4-field method. This algorithm provides better perceptual visual quality than other motion adaptive de-interlacing as shown by the experimental results

Reconfigurable architecture design of motion compensation for multi-standard video coding

This paper proposes a reconfigurable video decoder architecture of motion compensation for multi-standard video coding including MPEG-2, MPEG-4 and H.264. Through top-down design methodology, we analyze the motion compensation algorithm of the targeted applications and extract the commonality of motion compensation algorithms among the three different standards. To design a reconfigurable processing element to perform the integer-sample and fractional-sample interpolation operations to simultaneously support the main video standards, a regular data flow is arranged during the design space exploration. In addition, the bandwidth reduction strategies are also adopted to reduce the memory access times and power consumption of motion compensation operations for high bandwidth requirement, especially in H.264. The design implementation of the proposed architecture is synthesized using TMSC 0.18um technology library and can operate at 108HMz to achieve the real time motion compensation coding of 1920×1088 at 30 frames per second in the three video standards.

Low complexity and high throughput VLSI architecture for AVC/H.264 CAVLC decoding

This paper introduces a low complexity VLSI hardware architecture for entropy coding with increased throughput, based on the study of the statistical properties of the Context-based Adaptive Variable Length Coding (CAVLC) in AVC/H.264. These enhanced designs are due to the results of the statistical analyses, in which better symbol length prediction was achieved by breaking the recursive dependency among codewords for multi-symbol decoder implementation. The proposed CAVLC decoder can also easily meet real-time requirements for High Definition (HD) (1920×1080) applications, while the clock speed is operated only at 13 MHz under the best case scenario.

On the verification of multi-standard SoC’S for reconfigurable video coding based on algorithm/architecture co-exploration

Based on concurrent exploration of both algorithm and architecture, this paper introduces an efficient verification methodology that targets at comprehensive functional verification throughout different levels of design granularities for multi-format media SoCpsilas with applications in MPEGpsilas Reconfigurable Video Coding. We present a verification technique that minimizes the number of test patterns but at the same time covering multiple profiles based on the functional commonalities extracted from multiple coding standards. In addition, algorithmic complexity analysis and dataflow modeling are also used to gain insight into flexible video architecture at early design stage in facilitating more efficient verification environment. Furthermore, an isolation technique is also presented for independent verification of coarse grain modules in the system level. We have shown that this verification methodology can effectively enhance the reliability and efficiency of SoCpsilas with high complexity and reconfigurability.