Hee Kong Phoon

A Methodology for FPGA to Structured-ASIC Synthesis and Verification

Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address the verification issue with a methodology and fabric to directly tie FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. The most important aspects of this methodology are the use of physically identical blocks for difficult-to-verify PLLs, I/O and RAM and a structured re-synthesis of FPGA logic blocks to target cells that guarantees anchor points for easy formal verification

A Highly Compatible Architecture Design for Optimum FPGA to Structured-ASIC Migration

Structured-ASIC design provides a mid-way point between FPGA and cell-based ASIC design for performance, area and power, but suffers from the same increasing verification burden associated with cell-based design. In this paper we address a structured ASIC architecture fabric directly tie to FPGA prototype and functional in-system verification with a clean migration path to structured ASIC. Our goal is to leverage the power/delay/area benefits of structured ASIC technology vs. FPGA with a simple flow which maintains the benefits of FPGAs for ease of test, prototyping, characterization and pre-verification. We will go over the introduction of FPGA to structured-ASIC migration, the architecture of the logic fabric follow by the Lcell to Hcell mapping methodology which can eliminate the need of complicated verification effort and overview of the CAD flow.

High performance configurable distributed hybrid memory in structured ASIC

Block memory or custom memory is one of the most important features in the Structured ASIC design. But block RAM is not suitable to form small memory array and also limited to the pre-defined location. On the other hand, the distributed memory is one of the most important features in FPGA to support small size memory application and available anywhere across the chip. But the distributed memory is not applicable in traditional Structured ASIC design due to design complexity and area constraint. In this paper, we presented a novel distributed memory architecture for Structured ASIC, Hybrid RAM (HRAM). It is built using HCell, the Altera HardCopy Structured ASIC logic cell. It is hybrid because it provides the advantages from both block RAM and distributed RAM. The HRAM also created using an innovative hybrid flow which is the combination of conventional custom design flow and ASIC design flow [2]. The implementation strategy will be shown in details and also various advantages for the HRAM architecture will be addressed in this paper.