Hee Yeoun Kim

Development of microbolometer with high fill factor and high mechanical stability by shared-anchor structure

For the development of small microbolometer for mobile applications, new pixel design to enhance fill factor by sharedanchor structures is suggested and it can be possible to make a one anchor per unit pixel. Fill factor increases 10% more than that of normal unshared-anchor design. Amorphous-silicon based microbolometer has been fabricated with 64x64 arrays of 25um pixel size to verify proposed design. Mechanical flatness of shared-anchor structure is enhanced. Responsivity is enhanced from 1.08e+5 V/W to 1.23e+5 V/W due to the increase of fill-factor compared to unsharedanchor. There are no mechanical, electrical and thermal crosstalk problems with adjacent pixels.

Organic Chip-Scale Physics Packages for MEMS Atomic Clocks

The organic chip-scale physics package for MEMS atomic clocks with function of thermal management and magnetic field control is presented. The organic package consists of MEMS alkali vapor cell, vertical-cavity surface-emitting laser (VCSEL), photo-diode, and rigid-flexible organic frame for package. The alkali vapor cell is fabricated by conventional bulk-micromachining. For thermal management of vapor cell, the micro-heater and resistance temperature detector (RTD) are integrated on the glass lid of vapor cell by using Ti/Pt thin film with typical lift-off process. In order to integrate of MEMS vapor cell, VCSEL, and photo-diode, each device is mounted on the organic substrate with area of 1 cm2 and they are vertically stacked and inter-connected. To increase the thermal resistance of physics package, the rigid-flexible PCB is applied for the suspension of alkali cell and VCSEL. The FEA analysis resulted 1300 K/W of thermal resistance and temperature difference within 100mK. For magnetic field control, the Helmholtz coil and folded mu-metal foil are embedded into stacked PCB to generate C-field and magnetic shielding. The magnetic field gradient of proposed coil was 120nT/cm. The mockup of proposed organic chip-scale physics had a volume less than 1 cm3 and the electro-thermal analysis presented the power consumption of 50 mW for operating temperature of 80°C from room temperature under 20 mTorr of vacuum environment.

Electro-Thermal Modeling and Experimental Validation of Integrated Microbolometer with ROIC

This paper presents an electro-thermal modeling of an amorphous silicon (a-Si) uncooled microbolometer. This modeling provides a comprehensive solution for simulating the electro-thermal characteristics of the fabricated microbolometer and enables electro-thermal co-simulation between MEMS and CMOS integrated circuits. To validate this model, three types of uncooled microbolometers were fabricated using a post-CMOS surface micromachining process. The simulation results show a maximum discrepancy of 2.6% relative to the experimental results.

Optimization of Etching Profile in Deep-Reactive-Ion Etching for MEMS Processes of Sensors

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and SF6 gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and SF6 should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and SF6 were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, C4F8 content of 400 sccm, and a gas exchange interval of SF6/C4F8 = 2 s/3 s.

Wafer-level reliability characterization for wafer-level packaged microbolometer with ultra-small array size

For the development of small and low cost microbolometer, wafer level reliability characterization techniques of vacuum packaged wafer are introduced. Amorphous silicon based microbolometer-type vacuum sensors fabricated in 8 inch wafer are bonded with cap wafer by Au-Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity in a wafer-level. For the packaged wafer with membrane thickness below 100um, it is possible to determine the hermeticity as screening test by optical detection technique. Integrated vacuum sensor having the same structure as bolometer pixel shows the vacuum level below 100mTorr. All steps from packaging process to fine hermeticity test are implemented in wafer level to prove the high volume and low cost production.