HeeJong Park

System-level approach to the design of ambient intelligence systems based on wireless sensor and actuator networks

Wireless sensor and actuator networks (WSANs) have become pervasive and are used in many embedded and intelligent systems. However, the complexity of applications based on these networks is limited due to lack of tools for designing distributed systems on top of WSANs. In this paper, we present how a system-level programming language, SystemJ, is used to develop a middleware-free Ambient Intelligence (AmI) system. The system consists of a combination of Internet-enabled stationary and mobile WSAN nodes, which resembles an Internet of Things scenario. A distributed warehouse monitoring and control scenario with collaborating stationary and mobile WSAN nodes is used as a motivating example designed and implemented in SystemJ. This example demonstrates the capabilities of SystemJ for designing distributed AmI systems with inherent support for reactivity and composition of concurrent behaviors based on a formal model of computation, without the need for any additional middleware. The approach is compared with existing software agent, robotic and WSAN middleware approaches in designing the same type of systems.

Scheduling Globally Asynchronous Locally Synchronous Programs for Guaranteed Response Times

Safety-critical software systems need to guarantee functional correctness and bounded response times to external input events. Programs designed using reactive programming languages, based on formal mathematical semantics, can be automatically verified for functional correctness guarantees. Real-time guarantees on the other hand are much harder to achieve. In this article we provide a static analysis framework for guaranteeing response times for reactive programs developed using the Globally Asynchronous Locally Synchronous (GALS) model of computation. The proposed approach is applicable to scheduling of GALS programs for different target architectures with single or multiple processors or cores. A Satisfiability Modulo Theory (SMT) formulation in the quantifier free linear real arithmetic (QF_LRA) logic is used for scheduling. A novel technique to encode rendezvous used in synchronization of globally asynchronous processes in the presence of locally synchronous parallelism and arbitrary preemption into QF_LRA logic is presented. Finally, our SMT formulation is shown to produce schedules in reasonable time.

A heterogeneous multi-core SoC for mixed criticality industrial automation systems

The paper introduces a new multi-core SoC platform designed for industrial automation applications with mixed criticality. The applications are written in SystemJ language. The multi-core platform consisting of three different types of cores is implemented in a SoC that contains a standard dual-core ARM and a FPGA, which is used to run the critical part of the system. The platform is fully customizable in terms of number and types of cores to the needs of the application. An industrial automation case study is used to demonstrate the use and performance of the multi-core SoC.

A New Design Paradigm for Designing Reactive Pervasive Concurrent Systems with an Ambient Intelligence Example

Modern ubiquitous computing systems are created with large number of embedded sensing and actuation devices, which together form complex distributed collaborative systems. While the advancements in underlying embedded sensing, actuation and control technologies are tremendous, the system designers still lack proper software approach that can handle systems with complex and concurrent control flow on distributed networked infrastructure. In this paper, a system-level design language, SystemJ, which is based on a formal Model of Computation, is used to provide a new design paradigm for ambient intelligence systems. SystemJ has a set of kernel statements for modeling reactivity, preemptions and concurrency, which allow intuitive handling and composition of complex systems based on concurrent software behaviors. It also provides high level objects called signals and channels, to abstract away the underlying hardware devices and communication mechanisms. The run-time support of the language provides functionalities similar to middleware. An access and environment control system demonstrates the use of SystemJ in implementing typical reactive behaviors in ambient intelligence applications.

Optimizing Latencies and Customizing NoC of Time-Predictable Heterogeneous Multi-core Processor

The Time-Predictable Heterogeneous Multicore Processor (TP-HMP) is based on a NoC and fully implemented in a standard FPGA chip. The NoC uses TDMA-MIN interconnect with bounded latency, high throughput and low implementation cost. TP-HMP is used for execution of programs written in concurrent GALS language SystemJ suited for both soft and hard real-time systems. It uses two types of cores in different configurations and is suitable for static analysis of schedules that implement the program control flow and concurrency. The configuration and number of cores of both types used to achieve specific performance measures can be tailored/optimized for a given application. In this paper we focus on optimization of latency of TDMA-MIN NoC, which also results in mapping of processor cores on physical ports of NoC and optimal TDMA round. We also analyze the performance of TP-HMP execution of the benchmark program used in industrial automation case study.

FPGA-based Mixed-Criticality Execution Platform for SystemJ and the Internet of Industrial Things

This paper presents an extensible and adaptable platform for distributed applications with mixed criticality based on using state of the art FPGA technology. Although capable of executing programs written in different languages, the platform specifically targets the execution of programs written in Globally Asynchronous Locally Synchronous language SystemJ used in the context of Internet of Industrial Things. The key properties of the prototype platform are accommodation of mixed-criticality processing as well as provision of Internet addressable services. Mixed-criticality execution platform (MCEP) uses multiple processor cores and network interfaces: (1) a dual-core ARM processor with Ethernet for Internet access and processing of non-real -- time application parts and (2) TP-JOP reactive hard real-time processor with customized Controller Area Network (CAN) for real-time and time-critical response processing. This platform has been successfully developed and used in an industrial automation system within the Internet of Industrial Things context.

Compiling and verifying SC-SystemJ programs for safety-critical reactive systems

Most of todays embedded systems are very complex. These systems, controlled by computer programs, continuously interact with their physical environments through network of sensory input and output devices. Consequently, the operations of such embedded systems are highly reactive and concurrent. Since embedded systems are deployed in many safety-critical applications, where failures can lead to catastrophic events, an approach that combines mathematical logic and formal verification is employed in order to ensure correct behavior of the control algorithm. This paper presents What You Prove Is What You Execute (WYPIWYE) compilation strategy for a Globally Asynchronous Locally Synchronous (GALS) programming language called Safey-Critical SystemJ. SC-SystemJ is a safety-critical subset of the SystemJ language. A formal big-step transition semantics of SC-SystemJ is developed for compiling SC-SystemJ programs into propositional Linear Temporal Logic formulas. These LTL formulas are then converted into a network of Mealy automata using a novel and efficient compilation algorithm. The resultant Mealy automata have a straightforward syntactic translation into Promela code. The resultant Promela models can be used for verifying correctness properties via the SPIN model-checker. Finally there is a single translation procedure to compile both: Promela and C/Java code for execution, which satisfies the De-Bruijn index, i.e. this final translation step is simple enough that is can be manually verified. HighlightsIntroduction of safety-critical subset of the SystemJ language called Safety-Critical (SC) SystemJ.Automata-based compilation approach for the SC-SystemJ language.A tool-chain for verifying correctness properties (e.g. liveness and safety) of the SC-SystemJ programs and generating executable from the verified code for deployment.The new compiler generates both faster and smaller executable compared to the original SystemJ compiler.

The Cardiac Pacemaker: SystemJ versus Safety Critical Java

A cardiac pacemaker example is used to compare and contrast the Synchronous Reactive (SR) programming model of SystemJ with the SCJ programming model. Our pacemaker is implemented in the synchronous subset of the Globally Asynchronous Locally Synchronous (GALS) SystemJ, which extends the Java language with reactivity, concurrency and real-time constructs based on a formal mathematical framework. The use of different programming models results in different design choices and implementations. The SR programming model is driven by a logical clock, which clearly demarcates the state boundaries and is ideal for formal verification of functional and real-time properties. Unlike the preemptive scheduling model prescribed by the SCJ specification, the SystemJ program execution model is atomic and non-preemptive between two logical ticks, and as such it is statically schedulable without the need for a runtime scheduler. To check the effectiveness of the SystemJ approach, we implemented the cardiac pacemaker on three different execution platforms that demonstrate feasibility of guaranteed real-time of the pacemaker execution with a fraction of the used processors resources.

WYPIWYE automation systems — An intelligent manufacturing system case study

We present a novel approach for design of manufacturing automation systems with formal verification of selected properties based on the use of Globally Asynchronous Locally Synchronous programming language SystemJ and industrial-proof verification tools. By being able to prove properties of the automation control logic that consists of multiple concurrent controllers, represented by FSMs that correspond to asynchronous processes of SystemJ program, using Spin model checker, we demonstrate that the program features can be formally verified. Moreover, by also guaranteeing preservation of features and GALS model of the SystemJ program after compilation (correct by construction specification), we actually close the design process within What You Prove Is What You Execute (WYPIWYE) Paradigm.

GALS-CMP: chip-multiprocessor for GALS embedded systems

In this paper we present a novel multi-processor architecture for concurrent execution of programs that follow the Globally Asynchronous Locally Synchronous (GALS) formal model of computation. Programs are specified using the SystemJ concurrent programming language, suitable for modeling heterogeneous embedded applications that contain reactive and control driven parts and interact with the external environment. The proposed architecture is based on separating the control-driven and data-driven operations and executing them on distinct cores that support both types of operations, implemented as two modes within the single processor core. Each core can switch between two modes without any overhead. The core as the basic building block of the multiprocessor extends Java Optimized Processor (JOP), suitable for data-driven transformational operations, with control-oriented constructs that implement concurrency, reactivity, and control flow in SystemJ. Experimental evaluation over a range of benchmarks shows significant performance improvements over the existing platforms developed for the execution of the SystemJ program.