Heejong Yoo

LMS adaptive filters using distributed arithmetic for high throughput

We present a new hardware adaptive filter architecture for very high throughput LMS adaptive filters using distributed arithmetic (DA). DA uses bit-serial operations and look-up tables (LUTs) to implement high throughput filters that use only about one cycle per bit of resolution regardless of filter length. However, building adaptive DA filters requires recalculating the LUTs for each adaptation which can negate any performance advantages of DA filtering. By using an auxiliary LUT with special addressing, the efficiency and throughput of DA adaptive filters can be of the same order as fixed DA filters. In this paper, we discuss a new hardware adaptive filter structure for very high throughput LMS adaptive filters. We describe the development of DA adaptive filters and show that practical implementations of DA adaptive filters have very high throughput relative to multiply and accumulate architectures. We also show that DA adaptive filters have a potential area and power consumption advantage over digital signal processing microprocessor architectures.

Hardware-efficient distributed arithmetic architecture for high-order digital filters

The paper presents a new memory-efficient distributed arithmetic (DA) architecture for high-order FIR filters. The proposed architecture is based on a memory reduction technique for DA look-up-tables (LUTs); it requires fewer transistors for high-order filters than original LUT-based DA, DA-offset binary coding (DA-OBC), and the LUT-less DA-OBC. Recursive iteration of the memory reduction technique significantly increases the maximum number of filter order implementable on an FPGA platform by not only saving transistor counts, but also balancing hardware usage between logic element (LE) and memory. FPGA implementation results confirm that the proposed DA architecture can implement a 1024-tap FIR filter with significantly smaller area usage (<50%) than the original LUT-based DA and the LUT-less DA-OBC.

A continuous-time speech enhancement front-end for microphone inputs

In this paper, we propose a real-time noise suppression system implemented with analog VLSI. The algorithm implemented is designed to reduce stationary background noise while preserving the non-stationary signal component. Because the system relies on analog computation rather than digital, it has benefits such as extremely low power consumption and real-time computation. The algorithm is based on digital signal processing foundations that are slightly adjusted for use in the continuous-time domain. The analog components described as part of this system include a C/sup 4/ second-order section bandpass filter, peak and minimum detectors, a translinear division circuit, and a differential multiplier. Floating-gate circuits are used to set bias points and adjust offsets.

A novel high performance distributed arithmetic adaptive filter implementation on an FPGA

In this paper, an FIR adaptive filter implementation, using a multiplier-free architecture, is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed, low logic complexity LMS adaptive filter can be realized employing the proposed architecture.

An FPGA implementation for a high throughput adaptive filter using distributed arithmetic

In this paper, an FIR adaptive filter implementation using a multiplier-free architecture is presented. The implementation is based on distributed arithmetic (DA) which substitutes multiply-and-accumulate operations with a series of look-up-table (LUT) accesses. This can be achieved at the cost of a moderate increase in memory usage. The proposed design performs an LMS-type adaptation on a sample-by-sample basis. This is accomplished by an innovative LUT update using a matched auxiliary LUT. The system is implemented on an FPGA that enables rapid prototyping of digital circuits. Implementation results are provided to demonstrate that a high-speed LMS adaptive filter can be realized employing the proposed architecture.

A reusable distributed arithmetic architecture for FIR filtering

This paper presents a new hardware efficient distributed arithmetic (DA) architecture for high order (> 1024) digital filters. The new architecture is termed reusable distributed arithmetic (RDA). The proposed architecture has a linear dependence of memory size on filter length versus the exponential dependence found in lookup table (LUT)-based designs by removing the LUT and generating the required combinations online. In addition, the proposed RDA architecture reuses the computation blocks much like the way multipliers are reused in multiplier-based architectures to reduce hardware complexity. The proposed RDA design is compared against a multiplier-based (MM) design to illustrate the area dependency of both designs on filter length. FPGA synthesis results confirm that the RDA design is capable of much higher order filters (2048 tap) than the MM design (512 tap) while at the same time having similar equivalent gate counts and throughput.

A low-power system for audio noise suppression: a cooperative analog-digital signal processing approach

In this papec we innoduce the concepr of cooperative nnolog-digital signnlpmcessing, and its opplicalion in rhe developmenr of (I real-time noire suppremion system. 7he olgo”thm implememed is designed lo reduce staI i o n q background noise while preserving :he non-stalionam signal component 7he oigorirhm is based on digital signal processing fouridorions :ha: are slightly odjusledfor use in rhe cominuous-time domain. Because the splsreni relies on analog compulnlion mther lhon digital, it has benej t r mch as exrreniely low power consumplion and real-time compuraion. The onolog circuit elements am based on new~poatisg~gole circuits :hat ore small. eficient, mdprogrammable-akin8 i f possible to se: and tune bias points, dffsets, ondjlrerporomelers under digital conrrol. 1. COOPERATWE ANALOG-DIGITAL SIGNAL PROCESSING New advances in analog VLSI circuits have made it possible to perform operations that more closely reflect those done in DSP applications, or that are desired in future DSP applications [ I , 2, 3, 4, 5 , 6, 71. Fulther, analog circuits and systems can be pmgrummuble, reconfigurable, adaptive, and at a density compdmble to digital memories (for example, 100,000+ multipliers on a single chip) [ B , 9, IO, 1 I , 51. These properties have been almost exclusively associated with digital processing, but the addition of small, dense, programmable analog circuits provides a framework in which to create cooperative analogdigital signal processing systems that benefit from both approaches to make something better than the sum of its parts. We define cooperative analog-digital signal processing (CADSP) as the research field using combinations of programmable analog signal processing and digital signal processing techniques for real-world processing. Neither analog signal processing nor digital signal processing can exist in current technologies without the other; that is. realworld signals are analog while much of the modem control and communication is digital. Therefore, a primary question is where to parlition the analog-digital boundry to enhance the overall functionality of a system by utilizing analog/digital computations in mutually beneficial way (Figure I) . CADSP allows more freedom of movement for the partition between the analog and digital computation. CADSP is a superset of mixed-signal research in that it focuses heavily on algorithms as well as circuit implementation. By adding functionality to our analog systems, we enhance the capabilities of the controlling digital system, and therefore, the entire product under consideration. A full discussion of this partition problem can and will encompass several research papers. The range of applications for these approaches reaches from auditory and speech processing, to beam-forming, multidimensional signal ..... ~~~ ......... ~.~ . ...... ~...

On delay structures for the analog adaptive filters with long filter taps

Adaptive filtering of the time-domain signals requires delayed versions of the input signals. For example, adaptive filter for AEC (Acoustic Echo Cancellation) often has more than 1000 filter taps to correctly model a room impulse response. In analog-domain, first-order low-pass filters as well as the mixture of first-order low-pass and all-pass filter have been implemented for the approximation of ideal delay. In this paper, we investigate the accumulated noise problems of the analog adaptive filters that occur when nonideal delay filters are cascaded for a large number of filter taps. Group delay properties of various delay networks using low-pass and band-pass delay filters are also discussed.

C/sup 4/ band-pass delay filter for continuous-time subband adaptive tapped-delay filter

This paper describes the implementation of delay element using C/sup 4/ band-pass filter for subband analog tapped-delay adaptive filter, where implementation of larger group delay is required. Most analog delay elements have been implemented with low-pass and all-pass filters. While they can easily achieve constant group delay within pass band, maximum group delay is severely restricted by the corner frequency because group delay is inversely proportional to the corner frequency. We implemented a delay element with a capacitively-coupled current conveyor (C/sup 4/) band-pass filter to produce larger group delay required for analog subband adaptive filter. Experimental results from circuits fabricated in 0.5 /spl mu/m CMOS technology through MOSIS are also presented.