Heikki Kariniemi

Reusable XGFT interconnect IP for network-on-chip implementations

Platform-based design flows are coming into use in system-on-chip (SoC) circuit design. These design flows, which integrate different processors, large memory subsystems, reconfigurable logic blocks and reusable intellectual property (IP) blocks for various purposes into the same platform, use also reusable interconnect IP (IIP) blocks as communication infrastructures. This work presents a new layout scheme named Backbone layout where a new extended-generalized-fat-tree (XGFT) IIP can be used as a single large block. It is especially usable on such SoC circuits where IP blocks which communicate across the XGFT IIP are approximately of the same size. This paper presents also two different implementations of the XGFT HP and compares their performance. These two networks are also compared to a two-dimensional mesh which will be commonly used in network-on-chip (NOC) implementations. The results of the performance simulations and logic syntheses show that XGFTs are able to produce approximately the same performance as the mesh with considerably smaller area consumption. In addition, they show that XGFTs are more scalable for different performance requirements and different traffic patterns than meshes, and that the performance of the XGFTs and meshes can be improved by suitable placement of communicating blocks or software processes.

New adaptive routing algorithm for extended generalized fat trees on-chip

Network topology and routing algorithm are the issues that have the most significant effect on the performance of packet-switched networks. The throughput of fat trees can be considerably improved by connecting the topmost switches together and by replacing the most usually used minimal (shortest-path) routing algorithms with a new turn back when possible (TBWP) algorithm. This paper shows how the TBWP can also be used in extended generalized fat trees (XGFT) after the modification. The XGFTs are one version of fat trees with improved scalability. Simulation results are also presented so as to show the improved throughput of the modified XGFTs when the TBWP is used in them. This paper concerns also issues related to scalability.

Fault-tolerant communication over Micronmesh NOC with Micron Message-Passing protocol

In the future Multi-Processor System-on-Chip (MPSoC) platforms are becoming more vulnerable to transient and intermittent faults due to physical level problems of VLSI technologies. This sets new requirements to the fault-tolerance of the messaging layer software which applications use for communication, because the faults make the operation of the Network-on-Chip (NoC) hardware of the MPSoCs less reliable. This paper presents Micron Message-Passing (MMP) Protocol which is a light-weight protocol designed for improving the fault tolerance of the messaging layer of the MPSoCs where Micronmesh NoC is used. Its fault-tolerance is implemented by watchdog timers and Cyclic Redundancy Checks (CRC) which are usable for detecting packet losses, communication deadlocks, and bit errors. These three functionalities are necessary, because without them the software executed on the MPSoCs is not able to detect the faults and recover from them. This paper presents also how the MMP Protocol can be used for implementing applications which are able to recover from communication faults.

Arbitration and Routing Schemes for on-Chip Packet Networks

The operation of arbitration and routing algorithms has a significant effect on the performance of the packet switched networks. Switch arbiters, which are responsible for scheduling the internal resources of the switches for packet transfers from input ports to output ports, determine the throughput of the switch nodes. Their operation can be modeled with a bipartite graph matching problem where each maximum matching corresponds to a valid schedule with maximum number of simultaneous transfers. Arbitration algorithms can be classified to maximum size matching (MSM) and maximum weight matching algorithms (MWM). The MWM algorithms, which are able to take into consideration the filling of the input buffers, are usually able to produce higher throughputs than the MSM algorithms. In spite of this, most of the present arbiters implement the MSM algorithm or its approximation, because the MWM algorithms do not basically have fast and simple hardware implementations. For this reason, the beginning of this chapter, which concerns arbitration schemes, focuses mostly on the MSM algorithms. However, recent research results show such a progression that it can be expected that practical implementations for the MWM algorithms and their approximation may also soon become usable. Routing algorithms are responsible for controlling the routing of the packets to their desired destinations. The network topology, which can be either regular or irregular, affects the complexity of routing and restricts the set of usable algorithms. Generally speaking, routing in the networks with

NoC Interface for fault-tolerant Message-Passing communication on Multiprocessor SoC platform

A prevalent design paradigm in electronic systems design is the usage of multiple programmable processors on general purpose Multiprocessor System-on-Chip (MPSoC) platforms where processors and other sub-systems communicate through communication infrastructures called Network-on-Chip (NoC). This paper presents a new approach to a NoC Interface (NI) called Micronswitch Interface (MSI) designed for message-passing communication with a light-weight Micron Message-Passing (MMP) protocol on Micronmesh MPSoC platform. The operation of the MSI Hardware (HW) and Software (SW) are tightly coupled with that of the MMP protocol in order to improve communication performance. The MSI provides mechanisms for efficient buffer management and fault-tolerant communication which will be necessary for reliable and efficient operation of the MPSoCs. Performance analyses show that the MSI is also able to produce a good throughput and latency.

Fault-tolerant 2-D Mesh Network-On-Chip for MultiProcessor Systems-on-Chip

Large system-on-chip (SoC) circuits contain increasing number of embedded processor cores while their communication infrastructures are implemented with networks-on-chip (NOC). Due to the increasing transistor and wire densities these circuits are more difficult to test, which requires that different self-diagnosis and self-test methods must be mobilized. Self-diagnosis and self-repair methods usable for invalidating at least minor manufacturing defects of the NOCs may also be needed for improving the chip yield. This paper presents a new fault-tolerant NOC with two-dimensional mesh topology for future multi-processor SoCs (MPSoC). The improved fault-tolerance is implemented with fault-diagnosis-and-repair (FDAR) system, which makes the NOC more testable and diagnosable. The FDAR can detect static, dynamic, and transient faults and repairs the faulty switches. Furthermore, it makes it possible also for the local processors to reconfigure their switch nodes to work correctly. After the reconfigurations a novel adaptive routing algorithm named fault-tolerant dimension-order-routing (FTDOR) is able to route packets adaptively in seriously faulty networks. The usage of the FTDOR makes it also possible to use all of the ports of the edge switch nodes for connecting processors to the NOC, which improves the utilization of the NOCs resources

Micronmesh for fault-tolerant GALS Multiprocessors on FPGA

System-on-Chip (SoC) circuits have evolved to single chip Multiprocessor systems. Due to increasing variance of process parameters, which produces synchronization problems on large SoCs, a globally-asynchronous locally-synchronous (GALS) design style must have been mobilized. In addition, the large VLSI circuits are also becoming more susceptible to transient and intermittent faults which can corrupt their operation. This paper presents a new micronmesh network-on-chip (NoC) which is targeted to fault-tolerant communication of GALS Multiprocessor SoCs (MPSoC). It is fully synthesizable with current design tools and it can be used for prototyping MPSoCs on FPGA circuits. The Micronmesh incorporates a new improved fault-diagnosis-and-repair (FDAR) system which is able to diagnose and repair also buffer memories in addition to wire connections while fault-tolerant DOR (FTDOR) routing is used for routing packets to their destinations around defected parts. Owing to the FDAR system and the FTDOR Micronmesh degrades gracefully as permanent faults appear and it is able to recover from transient and intermittent faults. The fault-tolerance of the Micronmesh is also improved by switch-to-switch (S2S) level retransmissions which reduce the number of end-to-end (E2E) level retransmissions that produce considerably higher latencies. These methods targeted at improving the fault-tolerance are also becoming necessary for improving the manufacturability of the circuits in the future.

On-Line Reconfigurable XGFT Network-on-Chip Designed for Improving the Fault-Tolerance and Manufacturability of the MPSoC Chips

Large System-on-Chip (SoC) circuits will contain an increasing number of processors which will communicate with each other across Networks-on-Chip (NOC). The faulty processors could be replaced with faultless ones, whereas only a single defect in the NOC can make the whole chip unusable. Therefore, the fault-tolerance of the NOC is a crucial component of the fault-tolerance and manufacturability of the SoCs. This paper presents a fault-tolerant extended generalized fat tree (XGFT) NOC developed for future multi-processor SoCs (MPSoC). Its fault-tolerance is improved with a new version of fault-diagnosis-and-repair (FDAR) system, which makes it possible to diagnose and repair the NOC on-line. It detects such static, dynamic and transient faults which block packets or produce bit errors, and reconfigures the faulty switches to operate correctly. Processors can also use it for reconfiguring the faulty switch nodes after the faults are located with other test methods. Simulation and synthesis results show that slightly defected XGFTs are able to achieve good performance after they are repaired with the FDAR while the costs of the FDAR remain tolerable

High-performance NoC Interface with interrupt batching for Micronmesh MPSoC prototype platform on FPGA

This paper presents a new NoC Interface (NI) targeted for improving the performance of the Micronmesh Multiprocessor System-on-Chip (MPSoC). The previous version of the NI called Micronswitch Interface (MSI) can zero-copy messages as it sends and receives them. It offloads also some functionalities of the communication protocol from software (SW) to hardware (HW), but interrupt processing produces extra SW overhead and reduces the performance. For this reason, an improved version of the MSI called MSI-with-Queues (MSIQ) was designed with a new queue mechanism in order to reduce the frequency of interrupts and the SW overhead. Owing to the new queue mechanism of the MSIQ it is possible to batch and service multiple interrupt service requests by every execution of the Interrupt Service Routine (ISR). Additionally, the new MSIQ HW is able to send and receive messages while the processor is running the ISR. The performance of the MSIQ is also analyzed in this paper. The results show that the queue mechanism improves the performance with moderate hardware costs.