Helena Sarmento

Design of High-Speed Viterbi Decoders on Virtex-6 FPGAs

The Viterbi algorithm is one of the most popular algorithms for decoding convolutional codes. Implementing a high-speed Viterbi decoder is a challenging task due to the recursive iteration of an add-compare-select operation. In this paper, we propose and analyze several optimization techniques to improve the area/performance tradeoffs of high speed Viterbi decoders on Virtex-6 FPGAs. Both Radix-2, Radix-4 and a modified radix-4 add-compare-select units are implemented with these techniques. The implementation reports for a Virtex-6 FPGA indicate that the proposed techniques achieve very efficient designs of Viterbi decoders in terms of performance and area. 360 Mbps are achievable with radix-2 solutions, while radix-4 solutions can achieve 430 Mbps, better than previous state-of-the-art solutions. Higher data rates can only be achieved with other parallelization techniques, like the sliding block method.

A OFDM module for a MB-OFDM receiver

The rules defined by FFC, for marketing and operation of UWB products, permitted the use of orthogonal frequency division multiplexing (OFDM) to implement UWB communications. MB-OFDM is taking place as good approach to UWB, for instance for wireless USB. The latest generations of FPGAs, including DSP capabilities, embedded processors and special features for I/O streaming, are being efficiently used in wireless high-data rate applications. Therefore, FPGAs can be used for UWB technology implementation. This paper discusses the implementation of a specially tailored FFT to demodulate OFDM in a UWB receiver. Special emphasis is put on the design to fulfill the critical time requirements.

Implementation of a DAB receiver with FPGA technology

This paper describes the implementation of the main digital blocks of a DAB receiver. Hardware design is coded using HDL languages. Implementation is realized in a Virtex2 device. The integration of digital blocks, in order to implement a complete receiver, is analyzed

Tradeoffs in the design of sliding block Viterbi decoders for MB-OFDM UWB systems

MultiBand OFDM (MB-OFDM) UWB [1] is a promising short-range wireless technology for high data rate communications up to 480 Mbps. The UWB receiver uses a Viterbi decoder that must support the highest data rate of 480 Mbps. To achieve such high data rates a sliding block Viterbi decoder is a good design candidate. In this paper, we analyze the tradeoffs involved in the design of sliding block Viterbi decoders for the highest data rates of MB-OFDM UWB systems. We have designed a configurable transmitter/receiver of an MB-OFDM UWB system and an AWGN generator in VHDL and determined the bit error rates of the system running in FPGA. The results indicate the relation between bit error rates and different configuration parameters of the sliding block Viterbi decoder.

DCM demapper for MB-OFDM on FPGA

This paper presents the implementation of a dual carrier modulation (DCM) demapper, proposed as part of a MB-OFDM UWB receiver to be integrated in an FPGA. The implemented DCM demapper, together with the FFT and the Viterbi decoder, were implemented in a Xilinx Virtex-5 FPGA. The complete system was modelled and tested with Matlab/Simulink and the part implemented in FPGA was connected to Matlab using the System Generator from Xilinx.

FPGA implementation of IEEE 802.15.3c receiver

This paper presents the implementation of the OFDM demodulator and the Viterbi decoder, proposed as part of a wireless High Definition video receiver to be integrated in an FPGA. These blocks were implemented in a Xilinx Virtex-6 FPGA. The complete system was previously modeled and simulated using MATLAB/Simulink to extract important hardware characteristics for the FPGA implementation.

Sliding block Viterbi decoders in FPGA

In this paper, we analyze the design of sliding block Viterbi decoders in FPGA based on two proposed parallel Viterbi decoders with different area/performance ratios. Viterbi decoders for two wireless technologies were designed considering the proposed Viterbi decoders achieving reductions in resource utilizations of more than 50% compared to other state-of-the-art proposals1.

A 128 FFT core implementation for multiband full-rate ultra-wideband receivers

MultiBand OFDM (MB-OFDM) is a short-range wireless technology that permits data transfers at very high rates, between 53.3 and 480 Mbps. MB-OFDM uses the already licensed radio spectrum, between 3.1 GHz - 10.6 GHz, in an unlicensed manner, i.e. without a licensing cost or control. MB-OFDM divides the spectrum allocated to UWB into 14 bands of 528 MHz. Each OFDM symbol is transmitted across a band. The FFT processor is a crucial block in multi-carrier systems like OFDM, being responsible by the demodulation of the OFDM symbol. In this paper we discuss the design of 128-point Pipeline FFT modules optimized for use in OFDM based UWB receiver system to be implemented on a FPGA using Xilinx FFT CORE Generator.

A wireless biosignal measurement system using a SoC FPGA and Bluetooth Low Energy

This paper presents the development of a prototype for a wireless biosignal measurement system, which makes use of a System-on-Chip FPGA, with an embedded ARM processor, and the Bluetooth Low Energy standard for wireless data transmission to a smartphone. The body temperature and heart rate are monitored using a steel-head thermistor and an ECG acquisition module, respectively. The ARM processor runs a Real-Time Operating System. A part of the algorithm that extracts the heart rate runs on custom hardware implemented in the FPGA fabric. The prototype successfully extracts the vital signs and sends updated values to a smartphone every second.

Design of a multiband full-rate ultra-wideband receiver in FPGA

MultiBand OFDM (MB-OFDM) UWB [1] is a short-range promising wireless technology for high data rate communications up to 480 Mbps. In this paper, we have designed and implemented in an Virtex-6 FPGA an MB-OFDM UWB receiver for the highest data rate of 480 Mbps. To test the system, we have also implemented an MB-OFDM transmitter and an AWGN generator in VHDL and determined the bit error rates at the receiver running in an FPGA.