Helmut Schettler

Power-delay product minimization in high-performance 64-bit carry-select adders

This paper analyzes methods to minimize the power-delay product of 64-bit carry-select adders intended for high-performance and low-power applications. A first realization in 0.18-/spl mu/m partially depleted (PD) silicon-on-insulator (SOI), using complex branch-based logic (BBL) cells, results in a delay of 720 ps and a power dissipation of 96 mW at 1.5 V. The reduction of the stack height in the critical path, combined with the optimization of the global carry network with cell sharing and the selection of 8-bit pre-sums, leads to a reduction of the power-delay product by 75%. The automatic tuning of the transistor widths in 0.13-/spl mu/m PD SOI produces an energy-efficient 64-bit adder which has a delay of 326 ps and a power dissipation of 23 mW only at 1.1 V.

A study on bipolar VLSI gate-arrays assuming four layers of metal

Describes a design study on a bipolar gate-array or masterslice chip with almost 10000 circuits. It assumes 2.5 /spl mu/m groundrules and four layers of metal, i.e. three layers of metal for global wiring and one layer for power and I/O redistribution. It is proven by using actual logic from the IBM 4331 system, that an additional wiring layer increases the circuit density on a masterslice chip by more than a factor of 2. The paper is divided into three sections. Section 1 describes the chip design, the detailed arrangement of internal and external cells with the associated wiring channels and some general aspects of a masterslice design. Section II explains the placement and wiring tools and gives detailed results of a wiring study, comparing a logic design with 2 wiring layers with the same logic implemented with 3 wiring layers (4 layers total). Section III covers the off-chip communication with its associated problems like noise generation by simultaneous driver switching, three-state driver, and embedded RAM macro testing.

A CMOS mainframe processor with 0.5- mu m channel length

A processor chip set with IBM/370 architecture is implemented on five CMOS VLSI chips containing 2.8 million transistors with an effective channel length of 0.5 mu m. The chip set consists of the instruction and the fixed-point processor, two cache chips with 16 KB of data and instructions, and the floating-point processor. The chips are implemented in a 1.0- mu m technology with three layers of metal. An automatic design system based on the sea-of-gates technique and the standard cell approach was used. The worst-case operating frequency of the chip set is 35 MHz (typically 50 MHz). Four chips of the processor are packaged on a ceramic multichip module. Level-sensitive scan design, built-in self-test, and parity check guarantee high test coverage and reliability. >

Characteristics of a set of 12.7-mm processor chips

A 1.0-/spl mu/m CMOS technology with three layers of metal is used to implement a high-density master image that contains logic and RAMs. The image allows the use of more than 1,000,000 transistors. A hierarchical design methodology is described. This chip offers variable-sized physical partitions and RAM macros. Fixed area sizes and locations for partitions and macros are not necessary. Density and performance of custom chips are approached by the described methodology with significantly lower development cost and time.

Design of a branch-based 64-bit carry-select adder in 0.18 /spl mu/m partially depleted SOI CMOS

The paper presents the design of a 64-bit carry-select adder in Branch-Based Logic, a static design style that minimizes the internal node capacitances. This feature is used to lower the dynamic power dissipation, while maintaining good speed performances. The experimental realization of the adder demonstrates an overall delay of 720 ps while only dissipating 96 mW at 1 GHz. The fabrication is based on the 0.18 μm IBM CMOS8S2 SOI technology, which uses partially depleted transistors and copper metallization.

A mainframe processor in CMOS technology with 0.5 mu m channel length

A prototype of a processor chip set with a mainframe architecture is implemented using five CMOS standard cell chips. High performance is achieved by wide buses and a RISC- (reduced-instruction-set-computer) like implementation of frequently used instructions. The chip set consists of four units: (1) an instruction processor chip which fetches and decodes the instructions and contains the microcode storage; (2) cache chips which contain the address translation for up to 19 virtual address spaces, a four-way set-associative 16-kByte data/instruction cache, and a 32-B instruction buffer, which is loaded 16 B/cycle from the cache; (3) a fixed-point processor chip which contains the fixed-point registers and arithmetic and a second adder for the address calculation (base+displacement+index); (4) a floating-point processor chip which contains the floating-point registers, multiplier, and arithmetic unit. The processor is based on a four-stage pipeline (five stages for floating-point instructions).<<ETX>>